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19-Year-Old's Supercomputer Chip Startup Gets DARPA Contract, Funding
An anonymous reader writes: 19-year-old Thomas Sohmers, who launched his own supercomputer chip startup back in March, has won a DARPA contract and funding for his company. Rex Computing, is currently finishing up the architecture of its final verified RTL, which is expected to be completed by the end of the year. The new Neo chips will be sampled next year, before moving into full production in mid-2017.The Platform reports: "In addition to the young company’s first round of financing, Rex Computing has also secured close to $100,000 in DARPA funds. The full description can be found midway down this DARPA document under 'Programming New Computers,' and has, according to Sohmers, been instrumental as they start down the verification and early tape out process for the Neo chips. The funding is designed to target the automatic scratch pad memory tools, which, according to Sohmers is the 'difficult part and where this approach might succeed where others have failed is the static compilation analysis technology at runtime.'"
mean it.
Not sure whats more impressive, the fact that a 19 year old is able to get DARPA funding or the fact that a 19 year old (and his team presumably) is about to go into mass production with a fairly fancy looking custom microprocessor on a 28nm fab process.
I'd say that's a fair sign of success. Despite the sense of jealousy, nobody can think of anything bad to say
More like this site is slowly circling the drain. You know its bad when the trolls don't even bother.
That doesn't go very far in the microprocessor world. I worked for Cisco back in the early 00's and even back then tape out costs were approaching $1M for a 5 layer mask, today with sub-wavelength masks and chips using 12+ layers it must be tremendously expensive to spin a chip.
There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
Having received a contract from the same DARPA program it's nice to know who the competition is. Looks impressive
99.9999% of humans are stupider than this guy. How's that? Of course, ask him how much a candy bar is.
next coming up, six year olds...
It's just another VLIW chip promising that the compiler will take on the complexity being jettisoned from the hardware. *yawn*
We actually have very good reasons to say why this is a very different kind of VLIW, and have found the reason why other VLIW chips have had such static scheduling issues. Hope we can convince you and everyone else soon enough.
The final project of this VLSI elective course I took required each team to build three logical modules that would work together. I was responsible for the control and integration portion bringing together all the logical modules. I spent an entire sleepless night sorting out the issues. Our team was the only one that had a functioning chip (simulated) in the end. The lecturer wasn't surprised - most chips of any reasonable complexity require A LOT of painstaking (e.g. efficient routing, interference) work to get them working - often requiring certain modules to be pulled apart (or redesigned) so they integrate better with others.
Uhm, it ranges, but I'd say I can get a snickers bar for around a buck in most vending machines. And there are also plenty of people smarter than me, even in this very small niche that I am in.
When I was 19, my main achievement was building a bong out of a milk jug.
You are welcome on my lawn.
Good luck to you. The mighty Intel couldn't pull it off with the billions they sunk into Itanic but that doesn't mean it's impossible...just very very unlikely.
Execept everyone claims that their version is different and is going to solve all the problems of the previous VLIW chips. As I stated previously: *yawn*
But...but...this time it's different! Because...fairy dust and stuff!!
From what I've been able to read it doesn't look that different from other projects like Tilera or Kalray MPPA.
His chip has more fairy dust per transistor.
The biggest thing is what we have tried to emphasize, which is the fact that we have an entirely different memory system that does away with the hardware managed cache hierarchy. The rest of the really interesting stuff we have not publicly disclosed (yet), but I can tell you that it is very different from both Kalray and Tilera.
But what is very likely is that a bright teenager figured out how to suck money out of gullible, greedy stupid adults.
He does sound like a good snake-oil/tonic salesman.
"Virtual Memory translation and paging are two of the worst decisions in computing history"
"Introduction of hardware managed caching is what I consider 'The beginning of the end'"
---
These comments belie a fairly child-like understanding of computer architecture.
Parallella...
Please explain to me simply how you get 10x in compute efficiency over GPUs--these chips are already fairly optimal at general purpose flops per watt because they run at low voltage and fill up the die with arithmetic.
GPUs have excellent memory bandwidth to their video RAM (GDDR*), they have poor IO latency & bandwidth (PCIe limited) which is the main reason they don't scale well.
We've heard the VLIW "we just need better compilers" line several times before.
Thus far this sounds like a truly excellent high school science fair project, or a slightly above average college engineering project. It is miles away from passing an industrial smell test.
The biggest thing is what we have tried to emphasize, which is the fact that we have an entirely different memory system that does away with the hardware managed cache hierarchy. The rest of the really interesting stuff we have not publicly disclosed (yet), but I can tell you that it is very different from both Kalray and Tilera.
You might have answered this already but I'm not very good at reading walls-o-text, so apologies if this is a repeat: The hardware managed cache design for chips is popular for a reason - it provides a speed boost. If you remove this what kind of process do you propose to replace it with? (Unless you have a design that makes a hardware managed cache redundant. What do you do then? Have software manage the cache?)
I'm a minority race. Save your vitriol for white people.
"Why is there yogurt in this hat?" "I can explain that. It used to be milk, and well, time makes fools of us all."
I truly hope this approach pans out and advances chip design, but if it doesn't, it will be another publicly available learning tool for the next small team to learn from. It's easy to say that it won't work and that it is going down the same path as previous attempts, but thet might have something that does work and is worth a lot of money. If you don't like it, don't invest. If you think it has potential then pony up your own $100k and see where this goes. Either way a group of really smart people get to do some really cool shit, and as long as they don't get burned out or jaded by the online community, they all will be able to either continue on a successful project or regroup and tackle a new one. The whole world needs as many intelligent, ambitious, dreamers as possible...no matter what their inferred promiscuity / penis size is.
I, for one, assume any 19 year old willing to risk $1.25 mil can probably also pull a sizeable dong out of his pants during a funding presentation if needed.
Godspeed You! Black Emperor.
-jeff-
Including verification, a tape-out today is about $40M. Something doesn't add up here.
As somebody in the VLSI field, I am happy that somebody broke out of the monopoly/duopoly of the established players. WE are moving towards "single/double" vendor for everything from mobiles to laptop processors to desktop processors. Having little choice also harms progress.
The other thing which excites me is that you are going towards a completely new architecture. This is what innovation is about!
Hopefully, your success will inspire others also to take the plunge.
My Aurora : http://www.youtube.com/watch?v=o91ZsGwJYyg
FB : https://www.facebook.com/TanveersPhotography
Cue this old joke...
...
- How many hardware engineers does it take to change a light bulb?
- None, we'll fix it in software.
Doing stuff in software to make hardware easier has been tried before (and before this kid was born, perhaps why he thinks this is new). It failed. Transputer, i960, i432, Itanium, MTA, Cell, a slew of others I don't remember...
As for the grid, nice, but not exactly new. Tilera, Adapteva, KalRay,
The same guy?
http://www.flyertalk.com/forum/practical-travel-safety-security-issues/1695066-should-i-feel-unsafe-opinions.html
I take it "Rain Man" is before your time.
$100.
Most 19 year olds' idea of achievement is not puking up on the front doorstep after a particularly brutal night out boozing. For all you doubters: can we see how this chip performs in the wild before making judgement, please? To Thomas: will the chip ever see a retail shelf in say a personal supercomputer like the NVidia Tesla?
Political debates have me rolling my eyes so much I think I got optical whiplash. I should sue. - Foamy The Squirrel
Glad to see a post about serious computing for a change. I was getting pretty sick of the SJW bullshit.
1. We have already run through synthesis of a version of our core (and rough version of our chip)... There's a lot of work to be done, especially as we are in the last steps of locking down the RTL, but we are not worried about timing... we are being very conservative.
2. Already have standard cells and memory compilers. We are not amateurs.
3. We actually have solid state physics and fabrication experience, and understand the physical constraints of wire and gate delays, leakage, etc. All of those played a very large part in our architectural design, specifically so we don't have a timing and closure being a huge clusterfuck.
Take a look at my comment here: http://news.slashdot.org/comme...
The primary benefit of caches for HPC applications is *bandwidth filtering*. You can have much higher bandwidth to your cache (TB/s, pretty easily) than you can ever get to off-chip--and it is substantially lower power. It requires blocking your application to have a working set that fits in cache.
He's pulling out quotes from Cray (I used to work there) about how caches just get in the way--and they did, 30 years ago when there were very few HPC applications whose working set could fit in cache. It's a very different world nowadays.
Sometimes skipping college doesn't make you a genius, sometimes it just means you are doomed to repeat 50 years worth of mistakes in a well developed field.
Congratulations, trshomers!
Darned overloaded abbreviations. RTL has priority, means Resistor-Transistor Logic.
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Congratulations for tricking someone into giving you money. Good luck with your impending disaster.