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Intel Discloses Detailed Skylake Architecture Enhancements
MojoKid writes: Intel is still keeping a number of details regarding its complete Skylake microarchitecture and product line-up under wraps for a few more weeks, but at a public session at IDF, some of the design updates introduced with Skylake were detailed. Virtually every aspect of Skylake has been improved versus the previous-gen Haswell microarchitecture. I/O, Ring Bus, and LLC throughput has been increased, the graphics architecture has been updated to support DX12 and new eDRAM configurations, it has an integrated camera ISP, support for faster DDR4 memory, and more flexible overclocking features. All of these things culminate in a processor that offers higher IPC performance and improved power efficiency. There are also new security technologies dubbed Intel Software Guard Extensions (Intel SGX) onboard Skylake, which support new instructions to create and isolate enclaves from malware and privileged software attack, along with Memory Protection Extensions (Intel MPX) to help protect stack and heap buffer boundaries as well. A new technology, dubbed Intel Speed Shift, also allows Skylake to switch power states faster than previous-gen products, controlling P states fully in hardware, whereas previous-gen products required OS control. The end result is that Skylake can switch P states in 1ms, whereas it takes roughly 30ms with older processors.
If there was ever a true multi-threaded application AMD would take the prize. As such Intel dominates because of single threaded applications.
There are embarrassingly well-threaded applications where AMD does well. The x264 encoder does a fantastic job and hammers all 8 of the cores in my FX-8320 at >90% utilization, and it was cheerfully faster at that than the i5 3570K I used to keep around. But IPC does ultimately win out, and Haswell's AVX2 support is sufficient to let an i5 4690K generally pull out ahead of my FX. That's especially true on interlaced media, where the deinterlacer's essentially single-threaded and the rest of the chip's basically waiting for that single core to finish before tackling the rest of the workload. For most other uses it's somewhere around a Nehalem quad core: certainly fast enough for what I do, but the overall performance outside of niche applications isn't impressive in absolute terms. At least it took to undervolting well, and it's a friggin' behemoth for virtualization.
"Limited Liability Corporation" and "Internet Service Provider" don't make much sense, but then again I'm pretty far behind the times on CPU architecture. Who knows what coprocessors they're spending their insane transistor budgets on these days.
OK, "ISP" appears to mean "Image Signal Processor". "LLC" could mean "Last Level Cache" or "Logical Link Control". "Last Level Cache" makes more sense in context, though this is the first time I've seen that phrase. Usually cache levels are explicitly numbered (first, second, third, etc).
It looks like they spelled out everything else except "IPC" which is obviously(?) "Instructions Per Cycle".
Good job there, author, submitter, and editor!