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Intel Discloses Detailed Skylake Architecture Enhancements
MojoKid writes: Intel is still keeping a number of details regarding its complete Skylake microarchitecture and product line-up under wraps for a few more weeks, but at a public session at IDF, some of the design updates introduced with Skylake were detailed. Virtually every aspect of Skylake has been improved versus the previous-gen Haswell microarchitecture. I/O, Ring Bus, and LLC throughput has been increased, the graphics architecture has been updated to support DX12 and new eDRAM configurations, it has an integrated camera ISP, support for faster DDR4 memory, and more flexible overclocking features. All of these things culminate in a processor that offers higher IPC performance and improved power efficiency. There are also new security technologies dubbed Intel Software Guard Extensions (Intel SGX) onboard Skylake, which support new instructions to create and isolate enclaves from malware and privileged software attack, along with Memory Protection Extensions (Intel MPX) to help protect stack and heap buffer boundaries as well. A new technology, dubbed Intel Speed Shift, also allows Skylake to switch power states faster than previous-gen products, controlling P states fully in hardware, whereas previous-gen products required OS control. The end result is that Skylake can switch P states in 1ms, whereas it takes roughly 30ms with older processors.
I wonder if this Skylake can be considered an upgrade path..
That would violate Intels strategy, which is never allow a realistic upgrade path.
"His name was James Damore."
It's socket LGA 1151. New motherboard likely.
You'll need to wait for Skylake-E or whatever they will call it.
Sheesh. Skynet. They're going to call it Skynet.
Sounds like the last few generations - lots of incremental improvements and excellent technology but wont amount to much of a difference in general performance.
Sure looks like it
From the errata:
Executing CPUID with EAX = 7 and ECX = 0 may return EBX with bits [3] and [8] set, incorrectly indicating the presence of BMI1 and BMI2 instruction set extensions.
Attempting to use instructions from the BMI1 or BMI2 instruction set extensions will result in a #UD exception.
and in the errata summary, its currently labeled NO FIX so they dont even have a fix that will trap the exception and emulate the instructions (which would perform terribly anyways... but hey, working is better than not working.)
"His name was James Damore."
Intel's pricing (and refusal to offer 6-core mainstream parts) is a consequence of Intel's effective MONOPOLY in the x86 space. AMD's current CPU offerings are a BAD JOKE, offering around 50% per core of Intel's core performance. No serious PC gamer would opt for anything less than a true 4-core i5. AMD isn't even in the picture.
So why did I pay less for my i7 a couple of years ago than I did when I bought my Pentium-4 back in the days when AMD was actually competitive?
Intel's current competition is ARM, not AMD.
If there was ever a true multi-threaded application AMD would take the prize. As such Intel dominates because of single threaded applications.
There are embarrassingly well-threaded applications where AMD does well. The x264 encoder does a fantastic job and hammers all 8 of the cores in my FX-8320 at >90% utilization, and it was cheerfully faster at that than the i5 3570K I used to keep around. But IPC does ultimately win out, and Haswell's AVX2 support is sufficient to let an i5 4690K generally pull out ahead of my FX. That's especially true on interlaced media, where the deinterlacer's essentially single-threaded and the rest of the chip's basically waiting for that single core to finish before tackling the rest of the workload. For most other uses it's somewhere around a Nehalem quad core: certainly fast enough for what I do, but the overall performance outside of niche applications isn't impressive in absolute terms. At least it took to undervolting well, and it's a friggin' behemoth for virtualization.
If there was ever a true multi-threaded application AMD would take the prize. As such Intel dominates because of single threaded applications.
Actually, it still generally doesn't...
An Intel Core i7 generally is faster than a 8 core FX chip, even in really, really well threaded applications.
The Intel chip is SO MUCH better per core and with the help of hyperthreading, it still wins.
Of course, this is all a moot point, if you're serious about such work, you're at least on Haswell-E with 8 true cores and 16 threads, or you're on a Xeon and this isn't even a conversation worth having.
For pure speed, it is all Intel.
Historically and hysterically stupid post.
Yes, yours is. But what about mine?
Why would Intel not be charging more for a current i7 than they used to charge for a Pentium-4, if they had no competition? AMD has nothing in that market, and, even in lower-end markets, they barely compete on performance and are vastly more power-hungry.
If Intel started charging $1000 for an i3, the market would be flooded with ARM desktops by Christmas.
HOWEVER, what gamers want is a decent priced (sub 200 dollar) mainstream i5 with SIX true cores.
6 isn't enough of a jump over 4...
For most home / personal computing (including high end video games) diminishing returns kick in hard past 4 cores. The problem is that in the few cases where tasks can be easily subdivided so as to utilize more than 4 cores, the cores will normally be stuck waiting for memory updates which continues to lag (speed / throughput wise) behind processor compute ability at an increasingly large gap which spans orders of magnitude. Of course the only known way to speed DRAM is to utilize more power, which goes against the general IT development trends (greener computing, more capable mobile).
The processor to memory speed gap is one of the reasons why Intel is investing in novel memory technology (phase change memory, etc.). The recent XPoint memory announcement hinted at potential future usage as "page swap" memory, replacing virtual memory management swapping pages out to disk (mechnical or solid state).
I haven't read all of Intel's releases this week, but one area I'm interested in is seeing how eDRAM (embedded DRAM) aka Crystal Well technology is going to end up being available and utilized across the Skylake line. In memory intensive benchmarks eDRAM has already shown considerably improvement in memory constrained benchmarks in Broadwell mobile processors, wheere it acts as an additional level of cache.
Give me 8 true cores and 16 threads, remove the IGP which I don't need for such a CPU...
Most people don't utilize more than 2 cores for more than 25-33% of the time, so the market for consumer-oriented many core processors just isn't there. People who really need the performance already just buy a Xeon.
Intel's "hyper-threading technology" is one of the biggest disappointments in many years, I wish they would let the branding and feature set die in obscurity like it deserves (IMHO).
Yes, yes, I know, Xeon and Haswell-E, but the reality is that the "need" for 8 core chips won't really happen until more of them hit the desktop market, and what AMD sells as 8 core doesn't count.
Well 8-16 core processors have been around for what, a bit less than a decade now? They won't really happen in the consumer / desktop market, because the market isn't demanding it (with purchasing dollars, not wishful thinking). Look at the very modest take-up of the Haswell-E X99 (LGA2011) 6 to 8 core processors released last year (August-Sept 2014 IIRC).
I love fast computers, personally I have a 6 core i7-5930K, and the performance difference for most home/consumer applications is so trivial that I don't notice a difference over using a 4 core i7-4790K except for in parallel benchmarks.
"Limited Liability Corporation" and "Internet Service Provider" don't make much sense, but then again I'm pretty far behind the times on CPU architecture. Who knows what coprocessors they're spending their insane transistor budgets on these days.
OK, "ISP" appears to mean "Image Signal Processor". "LLC" could mean "Last Level Cache" or "Logical Link Control". "Last Level Cache" makes more sense in context, though this is the first time I've seen that phrase. Usually cache levels are explicitly numbered (first, second, third, etc).
It looks like they spelled out everything else except "IPC" which is obviously(?) "Instructions Per Cycle".
Good job there, author, submitter, and editor!