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IBM Scientists Find New Way To Shrink Transistors

Posted by samzenpus on from the getting-small dept.

MarcAuslander writes that IBM scientists have discovered a way to replace silicon semiconductors with carbon nanotube transistors, an innovation the company hopes will dramatically improve chip performance and get the industry past the limits of Moore's law. According to the Times: In the semiconductor business, it is called the 'red brick wall' — the limit of the industry's ability to shrink transistors beyond a certain size. On Thursday, however, IBM scientists reported that they now believe they see a path around the wall. Writing in the journal Science, a team at the company's Thomas J. Watson Research Center said it has found a new way to make transistors from parallel rows of carbon nanotubes.

5 of 100 comments (clear)

  1. Limits of Moor's law?? by trollingaround · · Score: 4, Informative

    The Moore law that I know says that the number of transistor in a IC, double approximately every two years. Is there another one that specifies some limits?

    1. Re:Limits of Moor's law?? by Alwin+Henseler · · Score: 2, Informative

      Physics? Or more specific in this case: how close atoms are arranged in typical semiconductor materials, and how few of them you need at a minimum to construct useful devices. That is: without practical issues like current leakage, isolation voltages, parasitic capacitance, etc, etc, making things not-so-useful (at best). Pro tip: try integer numbers first (or just very large numbers without counting exactly how many atoms go into your device).

      But please, if you know of a way to build IC's using 1/10-atom wide structures, I'm sure the engineers at IBM, Intel etc will be interested. After all, why let physics get in the way of human-invented 'laws'.

    2. Re:Limits of Moor's law?? by Anonymous Coward · · Score: 5, Informative

      There is a good reason why that buys you nothing, and costs you much: Basically, the thermal dissipation of a device of a given geometry is what gives it state, by thermalising the state change, it prevents quantum annealing from returning it to the previous or indeterminate state. To increase the number of states you have to increase the voltage proportionally to the number of states, so to add one extra bit (remember a bit is just log2(possible states)), you have to double the number of states, and therefore the voltage; all well and good? No, because the dissipation of a device is proportional to the square of voltage, so you have doubled the bit density by quadrupling the energy consumption of the device.

      And this is not even taking into account the added complexity (more gates) required to at some point discriminate these levels to implement logic. This also roughly scales to the square of the number of states. So you take the square of the square of the number of states, or raise the activation energy to the fourth power of what it was, at least making the device 8x more energy dense or less efficient for a 2x gain (this is the hard limit of information theory, real numbers are worse).

      Now there of course is still room at the bottom to make these quantum annealing devices we call switches more efficient, but the way you are proposing is working in the opposite direction.

      If you want a computer to be reliable, that is compute things much more often than uncompute things, you have to have a thermal bias, so that P(compute) >> P(uncompute), which we do by setting up an entropy gradient and periodically saving the result of some combinatorial equation to a register where it's value is constantly reinforced by that entropy gradient (current flowing through the latch), or else held in that state by lifting it over an activation barrier (as in memristors and Flash). Either way energy is consumed in the process, as you lift it into a indeterminate state and allow it to relax into the desired determinable state. The clock and Vdd provide together provide this energy to allow this to function.

      -puddingpimp

    3. Re:Limits of Moor's law?? by funwithBSD · · Score: 3, Informative

      Except that Moore's law has nothing to do with the size of transistors, but the number of transistors on a single chip.

      You can keep up by expanding the chip size, but then the yields tend to go down. If we could make perfect chips, the size could double every 2 years, although that would make for some very big chips indeed. Connections to the pinouts also become a problem as surface area expands faster than the perimeter.

      You could also go about it by making a true 3-d chip, instead of stacking individual chips on top of each other as they do today. That would make the external pinout problem even worse, as interior volume grows much faster than external surface area or edges.

      Shrinking the transistors is just the most effective way to do it, until you hit the red brick wall.

      --
      Never answer an anonymous letter. - Yogi Berra
  2. Crappy reporting is crappy by smaddox · · Score: 3, Informative

    The channel lengths were 60 nm. This is massive compared to the latest generation of CMOS (~14 nm).

    The confusion seems to come down to the fact that the SWCNT diameter is ~1 nm. However, 14 nm CMOS already uses FinFET's with channel widths of ~8 nm which is ~60 atoms.

    Regardless, the science article is actually about improved contact resistance, which is one of the major challenges associated with continued scaling of CMOS. However, they have only been able to show this improvement for p-channel devices, and they state clearly that n-channel devices present a much larger problem. If you want to replace CMOS, you need both n-channel and p-channel devices (not to mention fabrication yield needs to be as close to perfect as Si CMOS is). Thus my subject line (see above).