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IBM Scientists Find New Way To Shrink Transistors
MarcAuslander writes that IBM scientists have discovered a way to replace silicon semiconductors with carbon nanotube transistors, an innovation the company hopes will dramatically improve chip performance and get the industry past the limits of Moore's law. According to the Times: In the semiconductor business, it is called the 'red brick wall' — the limit of the industry's ability to shrink transistors beyond a certain size. On Thursday, however, IBM scientists reported that they now believe they see a path around the wall. Writing in the journal Science, a team at the company's Thomas J. Watson Research Center said it has found a new way to make transistors from parallel rows of carbon nanotubes.
Transistors, and their own US-based workforce.
The Moore law that I know says that the number of transistor in a IC, double approximately every two years. Is there another one that specifies some limits?
The summary doesn't say what size, and the article merely says "40 atoms in width" (presumable carbon atoms? Who knows?)
Apparently it's a technology that will coincide with the 7nm node.
"First they came for the slanderers and i said nothing."
I've seen tons of articles like this over the last decade, touting carbon nanotubes as being the enabling technology for all sorts of improved applications.
Can anyone actually point me to something that has made it to production utilizing carbon nanotubes? I'm not being snarky here - I'm really curious to know if any of this is actually getting off the workbench into mainstream use anywhere.
Carbon nanotubes hit me as being a wonder invention like nuclear fusion; if we can build it it will be awesome, but we probably won't be able to build it for at least $DATE + 20 years.
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The channel lengths were 60 nm. This is massive compared to the latest generation of CMOS (~14 nm).
The confusion seems to come down to the fact that the SWCNT diameter is ~1 nm. However, 14 nm CMOS already uses FinFET's with channel widths of ~8 nm which is ~60 atoms.
Regardless, the science article is actually about improved contact resistance, which is one of the major challenges associated with continued scaling of CMOS. However, they have only been able to show this improvement for p-channel devices, and they state clearly that n-channel devices present a much larger problem. If you want to replace CMOS, you need both n-channel and p-channel devices (not to mention fabrication yield needs to be as close to perfect as Si CMOS is). Thus my subject line (see above).
I think they meant "limits to Moore's law". Remember that Moore's law is not a law at all, it's just an observation. Furthermore, the observed doubling time has been steadily increasing for a number of years. Note that Intel missed their last targeted doubling.
The driving factor behind Moore's law has always been economics. Once scaling becomes too expensive, it won't happen (at least not at an exponential rate). We're getting close to that point. 3D transistors have delayed the end of Moore's law for NAND flash, but it's not clear if the same can be done for logic. Unlike NAND flash, the performance of logic circuits is usually limited by heat dissipation. If you go 3D, you might be able to pack in more transistors per unit area, but you can't operate all of those transistors at the same time or they will burn up.