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Intel Launches 72-Core Knight's Landing Xeon Phi Supercomputer Chip (hothardware.com)
MojoKid writes: Intel announced a new version of their Xeon Phi line-up today, otherwise known as Knight's Landing. Whatever you want to call it, the pre-production chip is a 72-core coprocessor solution manufactured on a 14nm process with 3D Tri-Gate transistors. The family of coprocessors is built around Intel's MIC (Many Integrated Core) architecture which itself is part of a larger PCI-E add-in card solution for supercomputing applications. Knight's Landing succeeds the current version of Xeon Phi, codenamed Knight's Corner, which has up to 61 cores. The new Knight's Landing chip ups the ante with double-precision performance exceeding 3 teraflops and over 8 teraflops of single-precision performance. It also has 16GB of on-package MCDRAM memory, which Intel says is five times more power efficient as GDDR5 and three times as dense.
Defects in the process bleeding edge process are the main reason to use the older process. When they make one of these insane multi-core parts the die size is very large (sometimes taking up a whole 26 by 32mm scanner field) thus the yields are hit harder by defects. On a more consumer level chip they may have 4 or more die in a scanner field. A single defect in this field will take out one of the four die resulting a a yield of 75% for that field. However in the case of a single die for the whole field the yield would be zero with the exact same number of defects per mm^2. I am sure they have a greater understanding of where their defects come from on the older 22nm process these days and can ensure good yields even with a huge die size.
An additional reason they would use the older process is a chip of this level of complexity probably requires tighter overlay and critical dimension (CD) control than the "standard" 22nm process to work well. Having a well defined process makes tuning all of these factors much easier and it also helps decouple if it was it the process or possibly a issue in the design when initial silicon runs do not work exactly as intended.
While supercomputing is a very small section of the computing world, it's not that hard to understand.
First of all, this would make for a terrible graphics card. This (deliberately) sits between a CPU and GPU. Each core in a Phi has more branching support, memory space, more complex instructions, etc than a GPU core, but is still more limited than a Xeon core (but it has wider SIMD paths).
A GPU has many more cores that have a much more limited set of operations, which is what is needed for rapid graphics render. But, those limited sets of operations can also very useful in scientific computing.
I haven't seen anybody try a three pronged approach (CPU/Phi/Nvidia Tesla), but I will admit I didn't look very hard. This is all in the name of solving really big problems.