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Thanks For the Memories: Touring the Awesome Random Access of Old (hackaday.com)
szczys writes: The RAM we use today is truly amazing in all respects: performance, reliability, price; all have been optimized to the point you can consider memory a solved problem. Equally fascinating is the meandering path that we've taken over the last half century to get here. Drums, tubes, mercury delay lines, dekatrons, and core memory. They're still as interesting as the day electrons first ran through their circuits. Perhaps most amazing is the cost and complexity, both of which make you wonder how they ever manage to be used in production machines. But here's the clincher: despite being difficult and costly to manufacture, they were all very reliable.
I suspect we may be nearing the end of DRAM, though only time will tell. DRAM is old and really a bottleneck these days, something is likely going to replace it. At the very least in the next few years the form factors will change from DIMMs to perhaps HBM stacked on-die and fiberoptic DIMMs. At least that would be my next guess, anyway.
Saying that a problem is solved is risky. Remember that the physics was solved shortly before Einstein et all! The future might reshape our perception, with for instance RAM and ROM convergence: https://en.wikipedia.org/wiki/...
One thing we have forgotten about is the impact (literally) of cosmic rays on memory cells. The old core planes were not very sensitive to the effect of an alpha particle from space zipping through the little donuts and changing values. But solid state RAM certainly was. In the old days, funny things would occasionally happen as a result of cells having their stored values flipped from 0 to 1 or back. These were rare random events that became more frequent as the amount of memory and its density grew. High reliability machines like servers used error correcting memory (ECC) that added a few extra bits so a change could be detected when the cell was read and hopefully recovered. The source of the problem is still there.. and so is ECC memory.
But here's the clincher: despite being difficult and costly to manufacture, they were all very reliable.
That was kind of built into the design spec. The guy who build unreliable memory (you know, the one who came up with the Alzheimer Machine) - well he went bankrupt pretty quick right alongside the guy who invented a horseless carriage that only needed a horse half the time.
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slower than even the slowest CPU cache.
CPU cache IS MEMORY, so how can it be slower than itself?
And before I quote the rest of your trash and make you look stupid, lets point out the most important fact here:
You can have RAM that runs as fast as CPU cache, you just can't afford it.. That CPU with 12MB of CPU cache is mostly expensive BECAUSE OF THE 12MB OF CACHE. and the difficulty in getting that much RAM to operate reliably at those speeds results in low yields, and increased consumer cost.
Even assuming we use the entire ~12MB of L3 cache as instruction cache (which is impossible really unless those instructions don't require any data access, which is utterly implausible), any modern CPU can blow through that in much less time than it takes a DDRx memory controller to set up a RAS.
Did you seriously imply that a Xeon CPU can blow throw 12MB of instruction cache in the amount of time it takes to do one complex instruction? That IS what you said. Which takes what? 40 clock cycles total, in the extreme worst case? (on anything with a 12MB cache which are going to all be high end/fast chips). So you're claiming that in 40 clock cycles it can empty a 12MB cache ... No. In 40 clock cycles ... it can load EXACTLY 40 registers with data from cache ASSUMING IT DOESN'T DO ANYTHING ELSE. So awesome, you just loaded 320 bytes of RAM into CPU registers ... and didn't use it for anything at all.
Do a BSR or BSF on 64 bit number takes 16 clock cycles all by itself!
The one and only thing slower than memory access is disk access, and even there we are closing the gap. Memory has not gotten appreciably faster in a decade, unless of course you ask marketing people.
DDR3's base rate is 800MT/s. DDR4's base rate is 2133MT/s ... yea, 2.5x is not appreciably faster or anything.
The one and only thing slower than memory access is disk access, and even there we are closing the gap.
Awe thats cute, you think SSDs are somewhere near RAM speeds. Just because SSDs are ridiculously fast at some things compared to spinning rust doesn't make them magically fast. We've had disks on arrays capable of saturating CPU bandwidth for years too.
This is literally the stupidest thing I've seen posted on Slashdot in a long time, since at least yesterday!
If you're referring to your post, then yes, I agree. It is pretty fucking stupid.
Do you know what DDR means? It means DOUBLE data rate. Twice as fast. (not really, but close enough for hand grenades). Do you have any idea what DDR2 did on top of that? And 3 ... and 4 ...
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Read up on what IBM did for their AS/400 architecture. Very brilliant work.
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The bit flips aren't due to neutrons, but to other high energy particles (cosmic rays).
And modern memory design tolerates this quite well (on chip EDAC, for instance).
But that's not the dominant source of errors any more. It's more things like electrical noise (signal integrity is another term). As you reduce the size of the device holding a single bit, you're starting to get down to where the thermal noise is a significant fraction of the "signal" (i.e. the presence or absence of charge in that bit storage).
I've heard some really interesting stories about Drum memory.
Since you had to wait for your desired read/write location to rotate under the head, and since this was back in the CISC era when the execution time of every instruction was known and published, developers would "optimize" their memory accesses by placing their data on the drum in the exact spot that each byte would be under the head when the instruction to read or write it was processed.
Even more interestingly, at least one platform made use of this architecture by using an assembly language that effectively had a goto at the end of every instruction. That way you could scatter your code on the drum to perform the same optimization.
I saw another story about early rotating-drum systems being put on USN ships. Supposedly the first time they tried to turn at sea the navigators discovered the hard way that the designers failed to account for the gyroscopic property of having a large rotating metal drum on board...
Apparently back in the day, core memory actually was a bit difficult to manufacture. Back in the 1960s, they wired the cores by hand and that apparently required quite a bit of manual dexterity. The first digital computer I ever saw was SWAC at UCLA (https://en.wikipedia.org/wiki/SWAC_(computer)). 256 37 bit words of Cathode Ray Tube memory. I have no real idea how it worked, but I recall that on days when it chose to work, there were a bunch of CRTs displaying an 8x8 matrix of zeros and ones. The professor in charge of the thing told us in his rather thick European accent that they were trying to augment the CRT memory with core, but that so far his graduate student(s) hadn't been able to thread the core wires well enough.
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"Random Access Memory (RAM) can only access one memory address at once. "
Random Access Memory can access memory randomly. The term includes no prior restraint on the number of ports. Internal caches are (typically) specifically SRAM, where you will note the "RAM" portion of the acronym.
"If you tried to use it for CPU cache, you would have to store the address of each cached word (collection of bytes) along with the value"
Caches already store the address of each cached word. This is the Tag RAM. Although once you are in the CPU you are typically operation on a portion of the address since the CPU internally can only access a portion of the address space at once. This portion is the Tag.
I actually have some core memory sitting in a box. I have no recollection now many bits, but it isn't all that many. When you (carefully) remove the cover, you see how small the individual elements are. The stories I heard back at the time were of Asian women with small fingers threading the wires through these things by hand.
Yep, I can verify that. Worked for Data General and the original Nova series used all core memory. The "core stacks" arrived in Mass from Asia and were then mounted on the memory card itself. Took the cover off of a dead one one time and it looked like velcro until I got it under a magnifying lamp. Even then, I was amazed at the dexterity it must take!
I have a 2" diameter jar with half a megabit of core memory, but it's not strung yet. They are extra-tiny cores. My coworker saved the core from a PDP-11 computer, I think it's 16k bytes. One board for the cores, one for the driver circuits.
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There's a video in the linked article that shows how core memory is made, and it is indeed a finicky manual process manipulating things to small for even pliers.
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