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The Secret to Tech's Next Big Breakthroughs? Stacking Chips (wsj.com)
Christopher Mims, writing for the Wall Street Journal: A funny thing is happening to the most basic building blocks of nearly all our devices. Microchips, which are usually thin and flat, are being stacked like pancakes (Editor's note: the link could be paywalled). Chip designers -- now playing with depth, not just length and width -- are discovering a variety of unexpected dividends in performance, power consumption and capabilities. Without this technology, the Apple Watch wouldn't be possible. Nor would the most advanced solid-state memory from Samsung, artificial-intelligence systems from Nvidia and Google, or Sony's crazy-fast next-gen camera. Think of this 3-D stacking as urban planning. Without it, you have sprawl -- microchips spread across circuit boards, getting farther and farther apart as more components are needed. But once you start stacking chips, you get a silicon cityscape, with everything in closer proximity.
The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.
The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.
In my EE grad class in 1998, we discussed chip stacking. Given the 2D manufacturing tech at the time (where chips are designed and manufactured in 2D then cut and seated in a larger housing), the biggest issue was literally how to bridge the 3rd dimension. Any imperfection in the wafer would mean an uneven seat when stacked. You have heat dissipation issues, which means a limitation in clock speed. And the simple act of aligning the layers at nm distances wasn't possible at the time. To get around this, you design a larger contact pad to allow for misalignment. The problem then was what happens when you have large plates in electric fields? That's right, capacitance, which screws up the expected voltage and creates resonance. It would revolutionize the industry, but there are a ton of technical issues to overcome.