The Secret to Tech's Next Big Breakthroughs? Stacking Chips (wsj.com)

Christopher Mims, writing for the Wall Street Journal: A funny thing is happening to the most basic building blocks of nearly all our devices. Microchips, which are usually thin and flat, are being stacked like pancakes (Editor's note: the link could be paywalled). Chip designers -- now playing with depth, not just length and width -- are discovering a variety of unexpected dividends in performance, power consumption and capabilities. Without this technology, the Apple Watch wouldn't be possible. Nor would the most advanced solid-state memory from Samsung, artificial-intelligence systems from Nvidia and Google, or Sony's crazy-fast next-gen camera. Think of this 3-D stacking as urban planning. Without it, you have sprawl -- microchips spread across circuit boards, getting farther and farther apart as more components are needed. But once you start stacking chips, you get a silicon cityscape, with everything in closer proximity.

The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.

Comments

Re:Many issues

[religionofpeas]

Here's an image:
http://electronicpackaging.asm...

As you can see, there's no need for nanometer alignment. Small imperfections aren't a problem either.

Re:Not really a new idea

[pz]

Indeed. I spent part of my doctoral work trying to understand the heat issues and trying to come up with solutions. Fundamentally, heat extraction is a surface-area process, whereas heat generation is a bulk process. Thus as you start to increase the thickness of the material, the heat, in general, goes up with the volume, or r^3, but the cooling capacity goes up with the surface, or r^2. If you start from an approximately planar structure, for a while, this is OK, but very quickly you run into trouble. The situation does not scale indefinitely without uncontrolled temperature rise.

One way of mitigating the issue when you are using a cooling fluid is to make the 3D structure porous, and flow the fluid through the device. We did just that. If relying on convection, you can fill the chip carrier with cooling fluid, and make a series of towers instead. We found the thermal latency was too slow for most applications in that case, but there were lots of assumptions that might have been incorrect for a specific situation.

If you are willing to flow coolant, then the obvious way to make it scale is to create a branched structure, not unlike blood vessels, where there is a central macroscopic pump that circulates the coolant through a network of finer and finer tubes until the heat has been extracted, and then through the inverse network of thicker and thicker tubes until you get back to the pump (and external cooling mechanism). Nature has this sort of arrangement all over the place.

My conclusion was that fundamentally 3D structures were going to have limited applicability without active cooling unless someone discovered the equivalent of room-temperature superconductivity for phonons (and thus heat) in an electrical semiconductor.