Intel's 10nm Cannon Lake CPUs Won't Arrive in Mass Quantities Until 2019, Company Says (pcgamer.com)

Intel said this week that it is once again delaying the mass production of its 10-nanometer "Cannon Lake" chips. The company insists that it is already building the chips in low volumes, but said it "now expects 10-nanometer volume production to shift to 2019 [rather than the end of 2018]." From a report: Intel is on solid footing, in other words, though pesky challenges remain in manufacturing its next-generation 10nm parts. CEO Brian Krzanich acknowledged as much during an earnings call, attributing the delay to difficulties in getting 10nm yields to where they need to be. So rather than push to ship 10nm in volume this year, Intel is giving itself some additional time to sort things out.

Comments

Thanks but no thanks, Intel

[Anonymous Coward]

It's AMD for my datacenter from now on.

Re:Thanks but no thanks, Intel

[Anonymous Coward]

"my datacenter "

I guess that's one way to describe that NAS full of Lolliporn, Chris.

Re: Thanks but no thanks, Intel

[Anonymous Coward]

You can't VMotion running VMs between Intel and AMD ESXi hosts. So it's not like I can just drop an AMD server into the cluster even if I wanted too. So, I'm kinda stuck with staying with Intel.

Re: Thanks but no thanks, Intel

[Narcocide]

Isn't it interesting how the solutions relying on the Microsoft ecology all seem to deadlock you to Intel hardware too, when none of the other virtualization technology seems to have that problem. I wonder if you've learned your lesson yet.

Re: Thanks but no thanks, Intel

[Anonymous Coward]

ESXi is VMWare not MICROSOFT.

Re: Thanks but no thanks, Intel

[art123]

This isn't a Microsoft specific issue. If a process is running on Windows or Linux and that process was using processor platform specific instructions (which it may have dynamically queried support for upon process startup) how is that process supposed to keep running on the other platform where the instruction doesn't exist?

Re: Thanks but no thanks, Intel

[sexconker]

You can if you fuck around with unsupported shit. I wouldn't trust it to work, however.
Of course, other hypervisors have no issue with this.

You're only stuck with Intel if you cannot afford brief downtime of a single VM. If you cannot afford that, you're in a precarious place regardless.

Re: Thanks but no thanks, Intel

[Megol]

VMware ESXi isn't part of the Microsoft ecology. It isn't based on Microsoft software.

I hope you learned your lesson - keep your mouth shut when adults are talking.

Re: Thanks but no thanks, Intel

[Anonymous Coward]

How other hypervisors wouldn't have the same issue?
The instructions sets called AMD-V and Intel VT-x are not the same.
I don't know how common is live migration on other hypervisors...

Re: Thanks but no thanks, Intel

[ckaminski]

VMotion doesn't require Windows. You can VMotion any supported OS.

https://partnerweb.vmware.com/programs/guestOS/guest-os-customization-matrix.pdf

Re: Thanks but no thanks, Intel

[ckaminski]

Which other hypervisors offer live migration across VM hosts?

Xen is the only other one I know about:
https://support.citrix.com/article/CTX115813

Q: Does XenMotion support live relocation of virtual machines between Intel-based and AMD-based host systems?
A: No, XenMotion supports live relocation of virtual machines between systems with the same type and manufacturer of processor.

Re: Thanks but no thanks, Intel

[Anonymous Coward]

*Your

Now hush little baby

Re: Thanks but no thanks, Intel

[sexconker]

What the FUCK about VMware requires Windows??????????

Re: Thanks but no thanks, Intel

[sexconker]

KVM does it.

Re: Thanks but no thanks, Intel

[b0bby]

That's cool, I use KVM quite a lot but I didn't know they supported that!

Re: Thanks but no thanks, Intel

[DigiShaman]

ESXi is it's own OS that runs the bare metal that's known as the host. The entire purpose of that OS is to be the hypervisor for all VMs that will run on it. Technically, ESXi is known as a Type-1 hypervisor. VMWare Workstation as an application that runs on Windows, that would be a Type-2.

Trivia time: Did you know that Microsoft Hyper-V is technically a Type-1. It's true. Hyper-V isn't a seperate application that runs on Windows; it gets away with being a Type-1 because it's part of Windows.

In regards to the AC post - He/she is correct. You can't VMotion a running VM in HA mode from AMD to Intel and vice versa. In fact, even in a pure Intel host cluster, the entire cluster is rated at the lowest common denominator in CPU generations. So if one of your host boxes has an older CPU, all hosts within that cluster must be configured to only use instructions sets of that generation. Conversely if you wanted to upgrade the CPU instruction set capability, you just replace that one host.

Re: Thanks but no thanks, Intel

[Anonymous Coward]

You are

Re: Thanks but no thanks, Intel

[DigiShaman]

Hyper-V does as well

Re:Thanks but no thanks, Intel

[Anonymous Coward]

"datacenter" ???

What happened to his "boxen" ?

Re: Thanks but no thanks, Intel

[Anonymous Coward]

And you are a fucking idiot... ESXi has NOTHING to do with Microsoft or Windows... shut the fuck up when you have no fucking clue

Re: Thanks but no thanks, Intel

[Highdude702]

Mod this fella up, +1 Informative. Wish I had mod points.

Re: Thanks but no thanks, Intel

[Anonymous Coward]

I pretty sure you are talking about vmware vcenter server. It's no more a requierment since the release of Vmware vcenter server appliance.

Re: Thanks but no thanks, Intel

[Anonymous Coward]

Lowest EVC mode if you didn't forget to set it up :D.

Re: Thanks but no thanks, Intel

[Anonymous Coward]

Agreed... no need to trouble yourselves intel. I am ONLY buying AMD from now on!

Re: Thanks but no thanks, Intel

[buchanmilne]

"You can't VMotion running VMs between Intel and AMD ESXi hosts. So it's not like I can just drop an AMD server into the cluster even if I wanted too."

Well, yes, you would need to create a separate cluster (managed by the same vCenter server), and shut VMs down to migrate between clusters. Oh the horror.

  "So, I'm kinda stuck with staying with Intel."

If you can't afford one reboot VMs one at a time, you have bigger problems.

Re: Thanks but no thanks, Intel

[Megol]

Either you are an idiot, a troll or someone incapable of reading simple text. What I wrote that was:

VMware ESXi isn't part of the Microsoft ecology.

It isn't based on Microsoft software.

Which means it have nothing to do with Microsoft _WHICH_WAS_THE_FREAKING_POINT_. It was a _CORRECTION_ of the post I responded to.

Suppose I shouldn't complain. Someone moderated me troll for the same post. Correcting an idiot poster by stating facts is now a troll...

But that's OK

[Anonymous Coward]

The anti-Luddite 3D printer revolution means I can download a CPU and 3D print one at home!

Re:But that's OK

[Anonymous Coward]

You have a 3D-printer that print cmos transistors? Where can I get one?

Will intel finally fix spectre and meltdown?

[Anonymous Coward]

They've had close to a year to work on it, and it's still a mess.

Intel in full damage control mode.

[Narcocide]

"No really guys. Don't buy that AMD chip yet. We promise that the next-gen chip we're making that will be so much faster than theirs really exists! We only need about 4 more quarters worth of earnings to prove it..."

Re:Intel in full damage control mode.

[capSAR]

Sounds like business as usual for Intel. I'm looking forward to trying out AMD for the first time, while they might not be perfect as a company I feel a bit better giving them my money.

Re:Intel in full damage control mode.

[Narcocide]

(Pro tip: try it with Linux!)

Re:Intel in full damage control mode.

[TheRaven64]

It's much worse than this:

First, these are Cannon Lake chips. Remember Cannon Lake, due late 2016? Delayed until late 2017? Delayed until late in the first half of 2018? Yup, that Cannon Lake. Among other things, Cannon Lake was scheduled to introduce LPDDR4, so would be the first Intel mobile chips that could manage 32GB of RAM without using a huge power budget. If you think it's bad for Intel now, wait for the Apple fanboys to notice...

Second, one of the features that people have been waiting for since it was originally announced in 2016 and was expected to debut with Cannon Lake is Intel's Control-flow Enforcement Technology. This comprises two parts. The first is a set of magic nops that indicate a valid branch target and protect forward control flow arcs (any jump that isn't to a designated landing pad will trap in code marked as supporting the feature). The second is a secure stack. Every call instruction pushes the return address onto the main stack, but also onto a second stack (which is not readable or writeable by normal instructions). Each ret instruction checks the top of both stacks and traps if they disagree. Sounds great? That's what everyone thought last year, but unfortunately it is incompatible with the retpoline Spectre mitigation that is now fairly widely deployed, so CET is now impossible to deploy in the presence of code using retpolines (e.g. Chrome) and so needs to be redesigned very late in the schedule or skipped entirely.

Re:Intel in full damage control mode.

[Anonymous Coward]

I'm not sure what kind of devices or software you have used that would have compatibility issues with AMD. I've run AMD from the Socket A era (skipped over the original FX series) and I can recall only a few times I've had compatibility issues with devices and not software. I've seen performance issues with devices on some AMD systems that worked great on an Intel system.

Re:Intel in full damage control mode.

[Anonymous Coward]

Interesting. Could you give an example? I haven't used AMD in many years either, but I never noticed compatibility issues in the past.

Re:Intel in full damage control mode.

[sexconker]

Really? Wow. That's interesting! Please detail 3 of these bizarre compatibility issues.

Re:Intel in full damage control mode.

[Anonymous Coward]

Quad core or desktop Cannon Lake was cancelled loooong ago, so now it's strictly a dual core / quad thread CPU for low power. Thus while this LPDDR4 support is great news it won't be suitable for Macbook Pro. When Cannon Lake production ramps up though it's suitable for the Apple "Macbook".

Yes I would like to see a high end Apple netbook with 32GB RAM lol, afterall I always run out of RAM way easier than I run out of CPU.
I bet the PCIe SSD has enough I/O to run slashdot with all its users.

Interesting will be if "Whiskey Lake" has LPDDR3 or LPDDR4 support. The former would be heinous but this might be yet another Skylake respin.
https://en.wikichip.org/wiki/intel/microarchitectures/whiskey_lake

Architecture
Key changes from Coffee Lake

        Package and pin-compatible with Cannon Lake U
        Die from Coffee Lake U and Cannon Lake PCH

Yea right I have a scoop for you. Whiskey Lake is still stuck with 16GB LPDDR3, if you want 32GB in a trendy laptop or a tablet you'll have to wait for Ice Lake in 2019, or hope someone does a Cannon Lake laptop or tablet with 32GB in 2019.

Re:Intel in full damage control mode.

[jwhyche]

. I'm looking forward to trying out AMD for the first time,

You won't be disappointed with AMD this go around. Take a look at the specs for the new 2700X.

https://www.cpubenchmark.net/c...

That is a $329 chip and has better performance than the closest intel chip in that class, the 8700K. The 8700K is also $30 bucks more. Sure there are more powerful intel chips but those chips are in the $1000+ range.

You can also find AMD chips in that range too but if you are going to do a bitch'n build and not break the bank the 2700X seems to be the way to go.

Re:Intel in full damage control mode.

[Anonymous Coward]

I've used a mix of Intel and AMD for my servers. I've found a slight longevity advantage to my Intel servers but overall both have been quite reliable and performant. I do a heavy mix of I/O and CPU bound tasks. Some machines are development machines and compile (yes, our code is in C) all day long while others are a mix of more standard server workloads (database, HTTP, application).

I don't think it matters all that much and we've found some cost savings in buying whatever is cheaper during our purchasing cycles. Support isn't really all that bad. If a machine has issues our software doesn't really care if it's an AMD or Intel box.

I would certainly encourage a mix of platforms. Eventually we'll even toss some ARM systems on our server side.

Re:Intel in full damage control mode.

[Anonymous Coward]

. I'm looking forward to trying out AMD for the first time,

You won't be disappointed with AMD this go around. Take a look at the specs for the new 2700X.

https://www.cpubenchmark.net/c...

That is a $329 chip and has better performance than the closest intel chip in that class, the 8700K. The 8700K is also $30 bucks more. Sure there are more powerful intel chips but those chips are in the $1000+ range.

  You can also find AMD chips in that range too but if you are going to do a bitch'n build and not break the bank the 2700X seems to be the way to go.

Don't forget that for that $329 you get 2700X and a really good CPU heatsink/cooler. Where as the 8700K costs $30 and comes with no cooler at all so you have to add another $50 for that.

Re:Intel in full damage control mode.

[ckaminski]

Can you elaborate?

Re:Intel in full damage control mode.

[jwhyche]

(Pro tip: try it with Linux!)

Okay. Lets see been running linux exclusively on AMD since the '486DX-133. Lets see, since that time I have run some variation of linux on every class of AMD processors. I have been running Centos on a AMD-8350 since 2012. In that time I have had exactly zero issue with linux and AMD processors.

Re: Intel in full damage control mode.

[Anonymous Coward]

Hackintosh or some other obscure OS perhaps? That is the only compatibility challenge I've heard of with AMD processors and to be fair Apple exclusively design their OS kernel and drivers with specific Intel models in mind and claiming compatibility issues with unsupported software is daft anyway. Just built a mid range Ryzen based system and very happy indeed with it, so far it's solid as a rock and blows my 3 year old i7 out the water in day to day tasks.

Re:Intel in full damage control mode.

[Anne Thwacks]

I am in Europe - we have had a Wine lake and a Milk lake for ages. No sign of Spectre, but I believe the Man from Uncle is still around somewhere (ITV2?)

Re:Intel in full damage control mode.

[Anonymous Coward]

8700K still is better in games, but the gap closed a bit.
The 2700X (or 2600X) will like fast RAM, but if you go with 16GB really fast RAM it'll cost you much.

Memory latency and cache latencies matter a whole lot for games.
This is where the 2700X beats the 1800X. Well, maybe it makes games 5% at the same clock, sometimes more but we have to scrounge for these 5% there and 5% here.
The $1000 Intel CPU? Now here is where it gets funny. This is an architecture made for servers with tons of cores, the bigger server variants have some 20 to 28 cores. Scaling to 28 cores was hard. These CPU have an all new, "meshed" floor plan which results in slower L2 and L3 caches.
This makes the $1000 Intel CPU (i9-7900X, etc.) slower in games!

In-game performance, three rough tiers from slowest to fastest :
- Ryzen 1700 to 1800X, Intel 7820X to 7900X - these all behave about the same, and a bit "slow", like older 2600K and 3770K sometimes
- Ryzen 2600X, 2700X
- i7 7700K or 8700K, depending (7700K has lots of GHz and low nanoseconds, but it's "only" a quad core)

But this might hardly matter.
I'd like a 2600X (kind of factory overclocked) with 2x16GB RAM. But RAM costs more than the CPU then.
Also I used to care about things above and thus read a couple reviews of the new CPUs but.. I miss when Windows XP was current and games didn't require the Internet. In fact I sometimes used to play games when I had no Internet or it was down. Duh!

If you do not play games perhaps get a 2700 without the X, and don't overspend on motherboard and RAM speed.

Re:Intel in full damage control mode.

[Tough Love]

There was the segfault issue with early Ryzen production, requiring an RMA. Inconvenient, but AMD handled it with good style. Then there wass the soft lockup at idle issue, apparently resolved by the new "typical power" option in recent bios updates. Otherwise, Ryzen has been really sweet, including for virtualization. It is fair to say that the Ryzen introduction was a little bumpy, but the overall experience is so positive (massive parallel throughput, decent single-core, great power efficiency) that the user community is happy to cut AMD some slack. It's a bit early to say, but I think my Ryzen systems are now in that "golden uptime" zen state. I certainly had that with my Piledriver + Radeon system - uptime measured in months, typically only limited by something like a power outage or a kernel update.

Windows users never noticed either of the above Ryzen issues, it's not clear why. Maybe, they just never put their systems under enough load to get the segfault, or it's hard to distinguish those segfaults from normal life in Windows land anyway. For the idle power issue, maybe AMD quietly supplied a fix to Microsoft months ago, ahead of users noticing it. Don't know. But it's water under the bridge now, I see no compelling argument to build an Intel box now or in the foreseeable future. With the Ryzen 12nm refresh already landed and 7nm parts scheduled to sample around the same time as Intel's roughly equivalent 10nm parts, it's clear that Intel has lost its process edge to TSMC and Glofo.

Of course the real elephant in the room at the moment is Meltdown. Intel does not have a credible answer, while AMD just designed their parts right in the first place. For the moment, if you want a system that is not just one gaping security hole, plus performs decently, AMD is the only game in town.

Re:Intel in full damage control mode.

[Tough Love]

if you are going to do a bitch'n build and not break the bank the 2700X seems to be the way to go.

If quiet is your thing, the 2700 is also a great choice. 65 watt envelope and even better value.

Re:Intel in full damage control mode.

[Anonymous Coward]

But with overclocking, you have to factor in the cost of better air and water coolers (varies in price from $50 to $150). And the serious overclockers delid. Not to mention the silicon lottery...

Still, Intel is probably the best bet for emulation of the Wii U and PlayStation 3.

Even the i5-8400 will get better framerates in games, but that really only applies if using a GPU stronger than a GTX 1060 (and/or the resolution is 1080p or below). Ryzen is competitive in all other tasks.

At the very least, AMD has managed to hold down the prices of Intel CPUs and eat into their profit margins.

Re:Intel in full damage control mode.

[edwdig]

The 8th gen Kaby Lake Refresh processors support 32 GB. Business oriented ultrabooks with 8th gen processors often have 32 GB as an option. Laptops like Thinkpads, Dell Inspiron, HP EliteBook, etc. It's just an option on customized orders. No one's mass producing laptops with that much built in, as the demand isn't there.

Re: Intel in full damage control mode.

[Anonymous Coward]

Let's hope that the recent mention of CannonLake-X was a typo.
I also wonder what chips are available to intels "special" customers, as insiders had skylake variants around two years before the consumer release...
As general-consumers we are all second rate in intels eyes it would seem.

Re:Intel in full damage control mode.

[jwhyche]

Thanks for bringing me up to speed. I was sniffing around Ryzen to replace my aging FX-8350 in my Centos box. I'm thinking that a 2700X would fit the bill.

Re:Intel in full damage control mode.

[Anonymous Coward]

This is likely DDR4 chips at 1.2 volt (or maybe lower, I don't know). I checked on ark.intel.com and the RAM limits haven't changed.
Umm, maybe these are laptops with RAM slots?

I have to make this more clear, as the thread has semi-implicit context.
The i7-8650 (e.g.) supports 16GB LPDDR3, or 64GB DDR4 (if a laptop or other machine is to have four slots)
The LPDDR3 is a kind of memory used on smartphone, which saves some amount of power - I don't know how much. Might be of interest when idle on battery. Smartphones have been using LPDDR4 or LPDDR4X. I bet it's smaller on motherboard too.

This is a major cause for rage about the Mac Book Pro. It also prevents a Surface Pro 5 with 32GB. If you just need to run some test set up of multiple VMs that are mostly idle etc. you're kind of stuck if it doesn't fit in the 16 or 8GB.

Re:Intel in full damage control mode.

[Anonymous Coward]

Of course the real elephant in the room at the moment is Meltdown. Intel does not have a credible answer, while AMD just designed their parts right in the first place. For the moment, if you want a system that is not just one gaping security hole, plus performs decently, AMD is the only game in town.

These are "alternative facts." They are not true.

The truth is that Intel was affected by Meltdown worse than AMD, but it is basically solved on both platforms by kernel patches. Spectre, the class of three different speculative execution bugs, affects Intel, AMD, and ARM, and it's not well-mitigated on any platform. Some patches went into the V8 compiler in Chrome, but that's about it. There's no general fix for it until we get new CPUs that do speculative execution less efficiently but more safely.

Moore’s law is dying

[Anonymous Coward]

Any advances in computing gets taken up by crypto miners leaving mainstream users with last gen chips. This means Intel just sits pumping out 14nm chips for years. Even Ryzen 2 is just a few percentage improvement over last gen. Until miners and phone companies get out of the chip game, expect more 14 nm chip generations to come from Intel.

Re:Moore’s law is dying

[Anonymous Coward]

Gibberish and faulty reasoning.

Re:Moore’s law is dying

[Holi]

what do general purpose CPUs have to do with cryptomining?
I don't know of any coin with any traction that uses CPUs, Bitcoin Lite Coin Dash etc are all ASIC mined and the Ethereum clones use GPU's. None of these will effect the sale of CPUs.

Re:Moore’s law is dying

[TeknoHog]

I don't know of any coin with any traction that uses CPUs, Bitcoin Lite Coin Dash etc are all ASIC mined and the Ethereum clones use GPU's.

Monero is #12 at Coinmarketcap, and it remains mine-worthy on CPUs. GPUs might be marginally more efficient, but they are within the same order of magnitude.

I'm not exactly vouching for Monero, as it's heavy and slow to use, even compared to its Cryptonote siblings, but it seems to have a lot of backing from the big boys. Also recently, ASICs suitable for Monero were released, and the Monero team reacted in a whack-a-mole fashion by changing some parameters in the proof-of-work algo. So not very professional, but as we know, the smartest tech doesn't always win the market.

Fabbing 10nm hasn't been easy

[Anonymous Coward]

TFA even alludes to this:

The company insists that it is already building the chips in low volumes..

That tells you all you need to know, really. The wafer-level fab process hasn't had high enough yields of functional dies to go into full-scale production to the point where they can sell them for a reasonable price. Them FETs are getting goddamned small!

Re:Fabbing 10nm hasn't been easy

[DontBeAMoran]

Or maybe they're telling us that Apple has paid in advance for all the Cannon lake CPUs Intel is able to produce right now?

Updated Mac mini and/or MacBook Air "soon"?

Re:Fabbing 10nm hasn't been easy

[omnichad]

Apple is in the middle of a full transition to their own ARM chips. And I doubt there will ever be another Mac mini. It's too much like a real, upgradeable computer.

Re:Fabbing 10nm hasn't been easy

[DontBeAMoran]

I doubt there will ever be another Mac mini. It's too much like a real, upgradeable computer.

They took care of that with the 2014 "update".

Re:Fabbing 10nm hasn't been easy

[Megol]

Citation needed. People have been talking about Apple switching to ARM for at least 5 years.

Re:Fabbing 10nm hasn't been easy

[omnichad]

I have no citation yet (Apple would try not to leak until the press event), but the momentum keeps building. The newest iMac Pro has an A10 Fusion chip for some functions (Macbook Pro runs the touchbar on ARM). Before, I think they were mostly driving that speculation themselves (and saving it as a backup plan) to keep Intel pricing under control. Now that AMD is more competitive, Intel will be looking to its major buyers to keep their profits up. Apple introduced bitcode to the OS X app store in 2015, meaning that for software that has this enabled, they can recompile (and even test) software for the new chip before the announcement without telling developers. On launch day, the app could be in the store on a new architecture without developers even updating it themselves.

Re:Fabbing 10nm hasn't been easy

[Anonymous Coward]

Citation needed. People have been talking about Apple switching to ARM for at least 5 years.

http://osxdaily.com/2011/05/06/apple-moving-macs-from-intel-to-arm-processors/

Re:Fabbing 10nm hasn't been easy

[ckaminski]

Exactly.

A switch away from intel will kill the performance users.

You'll lose them all to the surface books.

Re:Fabbing 10nm hasn't been easy

[angel'o'sphere]

Perhaps you want to enlighten us: in which cases is an Intel CPU faster than an ARM?

Re: Fabbing 10nm hasn't been easy

[Anonymous Coward]

A 7 year old article, nice.

Re:Fabbing 10nm hasn't been easy

[F.Ultra]

Especially those with Meltdown patches ;)

Re: Fabbing 10nm hasn't been easy

[Anonymous Coward]

Well, considering that I'm using some Mac Pros in a Mathematica cluster, ARM need not apply. Pretty sure my buddy doing video editing feels the same way.

Re:Fabbing 10nm hasn't been easy

[omnichad]

Apple hasn't released a true performance computer for a while - even their newest Mac Pro fails to keep up with the times.

The single core Geekbench scores of the Xeon e5 in the current Mac Pro match up not too far off from that of the A10X (with only a TDP of 8W). If Apple did a 10-12 core desktop chip with their A11X, they really could have the performance there.

Re: Fabbing 10nm hasn't been easy

[Anonymous Coward]

Most cases. Depends which models, obviously. Also depends on workloads but the A11 chip in the latest Jesus phones apparently bests some of the lower end Intel Core i3 desktop chips in geekbench. Would like to see more formal performance verification using multiple benchmarks though, as using just one tool can sometimes lead to biased results. My benchmark is how long it takes from cold boot to browsing porn, if I can use a mobile with one hand I might accept waiting a couple more seconds before seeing titties.

Re: Fabbing 10nm hasn't been easy

[DontBeAMoran]

The A11 in battery-powered devices where they need to keep the power requirements low and the heat dissipation to a minimum bests some of the lower end Intel Core i3 desktop chips connected to the power lines with massive heatsinks and fans.

We have no idea what kind of A11-style CPUs Apple has in its labs. For all we know, they have "A20" CPUs that can rival quad-core Intel i7.

Re:Fabbing 10nm hasn't been easy

[Megol]

In other words you got nothing.

Re:Fabbing 10nm hasn't been easy

[Megol]

This line of thinking is oversimplified: one can't just add a lot of stuff and expect everything to scale.

The interconnect between cores in a low power design with a few cores is different in a "manycore"* design designed for intermediary to reasonably high power (say 40-90W). To reduce the communication latency one will burn more power however Apple may try to keep a simple design and use NUMA type techniques to reduce longer latency communications in software.

Memory controllers would consume more, the GPU would probably be scaled significantly and thus consume more power. Just having a larger die means more power consumed (leakage and other effects).

Not saying an Apple processor couldn't provide a very good bang for the (power) buck compared to Intel processors but it isn't easy to compare a low power design with a higher power design.

(* relatively)

Re:Fabbing 10nm hasn't been easy

[omnichad]

It was really for an idea is performance scale, not literally using the same cores. They absolutely have been working on prototypes even if just as insurance against Intel pricing. The threat of being able to change architectures at the drop of a hat has served then well so far. But an educated guess still makes it likely that they will switch to ARM soon. There have been a lot of outwardly visible pointers.

Is "sort things out" an euphemism?

[sinij]

Is "sort things out" an euphemism for trying to patch gaping security holes?

Re:Is "sort things out" an euphemism?

[thegarbz]

Is "sort things out" an euphemism for trying to patch gaping security holes?

They have been sorting this platform out long before the gaping holes were first discovered.

Re:Is "sort things out" an euphemism?

[UnknownSoldier]

Marketing speak for "damage control".

Re:Is "sort things out" an euphemism?

[Anonymous Coward]

"sorting things out" means that 10 nm is not ready, which was to be expected if you've been following the progress in silicon feature size.

Re:Is "sort things out" an euphemism?

[DavidMZ]

No, semiconductor manufacturing has just gotten awfully complicated. If Intel haven't found yet a process integration scheme that gives an acceptable yield, they are not going to put it on the market and sell it for a loss.

Discloser: I work in the semiconductor industry

Re:Is "sort things out" an euphemism?

[Anonymous Coward]

It's funny how a previously-unknown security flaw dating back to the 90's gets discovered, and everyone starts jumping on the hate-Intel bandwagon, like it was some obvious thing that should have been addressed long ago. AMD spends over a decade doing absolute shit with product design, and now they're the Golden Child, lol.

You guys are as bad as the Chevy vs Ford people.

Re:Is "sort things out" an euphemism?

[Anonymous Coward]

More like, "wait until everyone forgets about these security holes we won't fix."

Re:Is "sort things out" an euphemism?

[Tough Love]

That, and trying to work EUV into the mix, really nasty stuff. Without EUV, multipatterning is a serious bottleneck.

Re:Is "sort things out" an euphemism?

[Tough Love]

Ah, and Intel seems to be way behind AMD in multi-die tech. Strategic blunder.

Re:Is "sort things out" an euphemism?

[Anonymous Coward]

You probably too young to remember Wintel conspiracy.

I don't understand

[Anonymous Coward]

I need Ray Kurzweil's opinion on this in order to get a better understanding.

Re: I don't understand

[Anonymous Coward]

And heâ(TM)s gonna say 2020

Re:I don't understand

[Anonymous Coward]

We're still reaching the singularity, but have crossed the event horizon. This means that time is slowing to a crawl. Ray Kurzweil was right but we'll reach the singularity in 10^140 years.

Alles Klar Kommissar

[hcs_$reboot]

So, the previous lineup Kaby Lake was also produced in low volumes, and this before the Spectre and Meltdown were revealed to the public, while Intel was aware... It seems 2018 is not the year they're gonna fix these two issues.

Re:Alles Klar Kommissar

[alvinrod]

They probably could fix those issues. The main hold up with the chips is that they've had no end of problems with their 10 nm process and it sounds as though there are still some substantial bugs to be worked out before they can go into full production. If they don't use this as an opportunity to fix the Meltdown/Spectre vulnerabilities, it would be a terrible mismove on their part.

Re:Alles Klar Kommissar

[TheRaven64]

Fixing meltdown is fairly simple - don't speculate across ring transitions. That will come with a small performance hit, but only a small one. Fixing Spectre is much harder because Spectre isn't really a vulnerability so much as a class of vulnerabilities with proofs of concept for the easiest things to attack. Fixing Spectre means making sure that no side effects of speculation, including timing, are visible. That means, among other things, no cache fills or evictions during speculative execution, all instructions in flight must be cancelled as soon as they're known not-taken, rename registers must be returned for use as soon as instructions are known to be cancelled, and so on. It might be possible to design a superscalar chip that is not vulnerable to Spectre-like attacks, but I'm sceptical (and I'm doubly sceptical that, if you could, it would perform better than an in-order processor).

Re:Alles Klar Kommissar

[rahvin112]

The best way to describe spectre is that's it's fundamental to how all out of order instruction processors work. All out of order processors will suffer from spectre.

Getting rid of spectre would require the return to in order execution at a MASSIVE performance penalty, more than 50% and probably closer to 75% drop in compute power. It's mitigateable but it's going to have hundreds of edge cases that will be found for years so it's going to take a long time (years) and a lot of rewriting in the fundamental parts of OS's to negate Spectre based attacks.

Spectre is fundamental to the design assumptions of all modern processors, as I like to say it's the bug that's going to give and give and give. They probably won't have found most of the edge cases until after 2020 so we should expect yearly/quarterly patches to spectre like attacks for a long time.

One thing that's not mentioned in a lot of the articles but the timing based attacks that comprise the spectre attacks were discovered years ago. It took several years for someone to find and demonstrate the first version of these attacks but most experts think this is just the beginning and that we're looking toward years of these type of attacks on all aspects of operating systems and CPU's.

In other words, spectre was just the first timing attack, there will be more, probably a lot more now that there is an actual example of how to do them.

Re:Alles Klar Kommissar

[TeknoHog]

Getting rid of spectre would require the return to in order execution at a MASSIVE performance penalty, more than 50% and probably closer to 75% drop in compute power.

Probably some dumb questions, but anyway:

(1) Does out-of-order necessarily imply speculative execution?

(2) Is in-order really that bad, considering all the other advances in processor design?

(3) What about efficiency? If in-order means the CPU is doing less work in a given time, is it also consuming less power? I.e. is the 50%..75% reduction in absolute computing power, or also efficiency?

(2) is related to some anecdotal experience that hyperthreading works well on in-order Atom processors. In my understanding, HT helps keep the pipeline full, so if it's half empty due to in-order design, the relative improvement would be better compared to OOO processors. (3) is also about pipeline utilization.

Did I mention I like the lack of these vulnerabilities on my Atom server? ;)

$ uname -p
Intel(R) Atom(TM) CPU D510 @ 1.66GHz
$ grep . /sys/devices/system/cpu/vulnerabilities/*
/sys/devices/system/cpu/vulnerabilities/meltdown:Not affected
/sys/devices/system/cpu/vulnerabilities/spectre_v1:Not affected
/sys/devices/system/cpu/vulnerabilities/spectre_v2:Not affected

Re:Alles Klar Kommissar

[Anonymous Coward]

Fair questions.

(1) No. For instance, if you multiply two registers, and then load a constant, two things that have only one outcome, you can run them both in parallel and finish the second one first.

However, OO really come into its own when coupled with speculative execution, because a lot of instructions can trigger faults. Anything to do with memory, for a start. That's when it becomes really useful to be able to speculatively execute past the possibly troublesome instruction, expecting there won't be a problem (which is usually the case), and rolling back otherwise.

(2) Yes, but it depends on the workload. If in-order means you can cram more cores, and that suits the workload (GPUs, ahem), then it's actually better. In general, it's bad, though.

(3) Absolutely. That's why low-power ARM designs use in-order, but high-performance ones use out-of-order.

Re:Alles Klar Kommissar

[Anonymous Coward]

I think that question 2 is the most interesting. The answer is that CPU's haven't really advanced meaningfully in many, many years. Most of the improvements have come from symmetric multiprocessing and lots and lots of optimizations, many of which are reliant on speculative and out of order execution. Some workloads can't be further parallelized and are actually less performant on today's chips than they were a few years ago as per-core performance has necessarily decreased.

In short, the limits of current processor design was reached years ago and the industry has instead been driven to parallelization and dodgy hacks to get further improvements. As a result, the focus shifted to reducing size and energy use.

It is likely that a fundamental shift would need to take place in CPU materials to see the performance leaps we have become accustomed to.

Re:Alles Klar Kommissar

[Anonymous Coward]

Xbox 360 CPU was in-order and used hyperthreading. It was power hungry, though! But maybe it's because it was a bad CPU, and was in 2005 with many peak gigaflops.

(2 bis) HT or more generically, SMT also has excellent results on OOO processors, at least the modern ones from the past decade. It helps fill up the execution resources like SSE2, AVX units
Perhaps in-order would work very well in similar situations, peak flops for "easy" scenarios like sound or image processing, 3D rendering.. You can even have 4-way SMT.
Otherwise when the workload makes it suck the performance will suffer.. Such that I tend to thick that on a big, high performance CPU, power use might be worse if an in-order CPU at 4GHz does the work an out-of-order CPU would do at 2.5 or 3GHz.

Re:Alles Klar Kommissar

[TheRaven64]

(1) Does out-of-order necessarily imply speculative execution?

No, though typically you move to speculative execution before you move to superscalar. Speculative execution is required to get decent performance from any pipelined processor. The difference between the speculative execution in a superscalar and an in-order pipeline is one of degree, rather than kind. There's a fairly common heuristic that you have a branch roughly ever 7 instructions in code compiled from vaguely C-like languages (code that is often quite misleadingly called 'general-purpose' code). If you have a 7-stage pipeline (fairly small by modern standards), then by the time you've got the first last instruction in a basic block out of the pipeline, you'll have reached the end. You now have two choices: wait until you have the branch target value (i.e. you've finished executing the instruction that computes it) or guess. If you guess and get it right even some of the time, you'll have better performance because you'll be executing useful instructions at least some of the time, whereas if you don't guess you're guaranteed to be executing nothing. This is the essence of branch prediction.

(2) Is in-order really that bad, considering all the other advances in processor design?

That depends a lot on the workload. GPUs, for example, are in-order and don't do speculative execution. They are really fast. They are; however, very slow at running typical C code.

Out of order designs result from the desire to exploit instruction-level parallelism. The basic idea is that it's easy to do things in parallel in hardware: just stamp out more logical blocks. Given sequential code, if you can convert it into sequences of data dependencies, you can then execute anything in parallel once its dependencies are satisfied. Most straight-line code has on the order of 4-way instruction-level parallelism, so if you can fully exploit this then you can run at around four times the speed.

The obvious alternative is to just have four single-pipeline[1] cores. This will give you better power efficiency, but at the cost of requiring some combination of the programmer and the compiler to generate code that exposes parallelism. You can take this even further and have multiple thread contexts per core, so whenever you would have to speculatively execute an instruction, you instead pause the thread and start running instructions from another thread. This approach means that all of the instructions that you're executing are ones where the result is actually used and simplifies some of the very complex parts of a processor (branch predictor, register rename engine) and so gives much better performance per Watt and per unit area than an out-of-order processor. If you have a source language that makes it easy to expose this kind of parallelism, then this will give you much better performance. Unfortunately, most Algol-derived languages (C, C++, Java, and so on) are not in this category.

(3) What about efficiency? If in-order means the CPU is doing less work in a given time, is it also consuming less power? I.e. is the 50%..75% reduction in absolute computing power, or also efficiency?

Good question. If you look in a typical Android smartphone, you will see ARM cores in a big.LITTLE configuration: a cluster of simpler in-order cores and a cluster of higher-performance out-of-order cores. The in-order cores will consume less power than the big cores executing the same sequence of instructions[2]. The peak performance for the big cores will be much higher, but at the cost of efficiency.

(2) is related to some anecdotal experience that hyperthreading works well on in-order Atom processors. In my understanding, HT helps keep the pipeline full, so if it's half empty due to in-order design, the relative improvement would be better compared to OOO processors. (3) is also about pipeline utilization

Pu

Backdoors?

[Anonymous Coward]

How many backdoors will they have?

Should be called .40 nanoinch CPUs

[Anonymous Coward]

n/t

Nobody wants a defective product in mass qty

[Anonymous Coward]

Is meltdown defect addressed in hardware for Cannon Lake or does Intel plan on knowingly releasing more defective product?

Re:Nobody wants a defective product in mass qty

[sexconker]

"Addresses in hardware" will mean "performance-fucking changes to built-in microcode" for at least another full generation.

Actual hardware fixes will also result in performance drawbacks. The whole issue is that they're executing and caching results before a simple security check. They've either got to stop that speculative execution, add a delay / wipe that prevents speculative results from being cached, or never let it hit the cache in the first place. All options incur a significant performance penalty for many operations.

Re:Nobody wants a defective product in mass qty

[Anonymous Coward]

"Addresses in hardware" will mean "performance-fucking changes to built-in microcode" for at least another full generation.

So then is the answer no it won't be addressed in Cannon Lake? I can't find any authoritative information on this.

Actual hardware fixes will also result in performance drawbacks.

Obviously there are always "performance drawbacks" to enforcing coherent operation of any hardware and software.

When I spend money I expect a faster product without known flaws. It would be nice to know in advance if Intel intends to deliver or not.

Re:Nobody wants a defective product in mass qty

[F.Ultra]

But with a proper fix in the CPU the performance penalty will be significantly lower than the current software work-around. And Intel have said that they will introduce chips with proper fixes in late 2018 so apparently they are working on it.

Re:Nobody wants a defective product in mass qty

[billyswong]

I guess proper hardware fixes will constitutes new instructions (or new ring), so that a user-mode program can tell the CPU which part of codes are from untrusted internet and to be further sandboxed against side-channel attack, while code not crossing the boundary can be kept high-performance.

Re:Nobody wants a defective product in mass qty

[Anonymous Coward]

That "late 2018" was what Intel said in January, before the 10nm delay was made public. So I wouldn't rule out that the fix was intended to be in those 10nm parts based on the Icelake architecture, and is not there in the new ones. But at least the new ones will likely have the same microcode "fixes" for Spectre built in from the start (but likely more or less the same fixes that past CPU's got in the form of microcode updates). But we'll see!

Re:Nobody wants a defective product in mass qty

[F.Ultra]

It was in March that they said that it would come in the second half of 2018 in the Cascade Lake architecture.

Meanwhile...

[Anonymous Coward]

14nm has become 70% more compact since the first 14nm products, which translates into whatever mix of power saving or performance increase you use it for.

Things have not stood still. 10nm will be another incremental step relative to 14nm.

The Xnm description of processes has become a tool of obfuscation. Gates per square micron might be better.

No shit it's delayed

[Anonymous Coward]

12nm was delayed by several years as well, and 10nm was supposed to be right on schedule?
Yeah right.
Moores law is dead, and all intel is doing is trying to prevent everyone from realizing it.

Do I hear 2020

[oh_my_080980980]

LMOL you were suppose to release this back in 2016. Maybe you should call IBM, they can show you how to do it :)

this is going to be a huge comment that will explo

[Anonymous Coward]

http://www.testingtur.com

here

Remember the shitpile of Intel.

[Anonymous Coward]

I will pick AMD chips for my datacenter.

I hope that AMD will win the 5nm race soon!. They will win money and technology in lesser time.

Three signs of wait, wait, wait are a waste of time and luxury availability.

The performers will be happy with this 5nm race.

Also,PCIe lanes, baby!

[Anonymous Coward]

PCIe lanes, all you can eat!