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DARPA Invests $100 Million In a Silicon Compiler (eetimes.com)
The Defense Advanced Research Projects Agency (DARPA) will invest $100 million into two research programs over the next four years to create the equivalent of a silicon compiler aimed at significantly lowering the barriers to design chips. "The two programs are just part of the Electronics Resurgence Initiative (ERI) expected to receive $1.5 billion over the next five years to drive the U.S. electronics industry forward," reports EE Times. "ERI will disclose details of its other programs at an event in Silicon Valley in late July." From the report: Congress recently added $150 million per year to ERI's funding. The initiative, managed by the Defense Advanced Research Projects Agency (DARPA), announced on Monday that the July event will also include workshops to brainstorm ideas for future research programs in five areas ranging from artificial intelligence to photonics. With $100 million in finding, the IDEAS and POSH programs represent "one of the biggest EDA research programs ever," said Andreas Olofsson, who manages the two programs.
Together, they aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs "will change the economics of the industry," enabling companies to design in relatively low-volume chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable, said Olofsson.
Together, they aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs "will change the economics of the industry," enabling companies to design in relatively low-volume chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable, said Olofsson.
As a former lead ASIC designer, I can say this is one of the most ambitious projects likely ever undertaken in EDA. Companies like Cadence, Mentor and Synopsys have been working on these problems for literally decades now. Everyone wants an easy solution for push-button design, but it is hardly that simple. Consider the following:
- Synthesis from RTL-to-gate level
- Functional design rule checks
- Place and route, including clock routing, PLLs/DLLs, etc.
- Timing extraction and static timing analysis
- I/O/SSO and core power
- Internal signal integrity and re-layout
- Test insertion and test vector generation
- Formal verification
- Functional verification
- Packaging and ball-out/bonding, especially with core I/O
- Physical design rule checks / Netlist vs. layout checks
A suite of tools that does all of this costs into the millions of dollars today, and is really a subscription as there are always bugs and improvements to be made. It also assumes physical design rule decks from the silicon vendors that have gone extensive characterization on limits such as minimum feature widths and notch rules can yield to a sufficient level economically, and that the gate and hard IP/mixed IP libraries have been validated. Front end functional design often requires re-architecture due to considerations when physically implementing the chip. All of this, of course, presumes that we don't run into additional phenomena that were irrelevant at larger process nodes (e.g. at ~250nm/180nm, wire delay dominated gate delay, and at 90nm/65nm, RC signal integrity models gave way to RLC, plus power/clock gating, multi-gate finFETs vs. single-gate planar past 22nm, etc.).
A push-button tool would have to take all of this into consideration. But let's face it...as well-intended as this is, you probably need another couple of orders of magnitude of money thrown at this to even begin succeeding under the fundamental assumption you don't have additional phenomena like alternatives to manufacturing. And that's the fundamental catch that is not captured in the article: we are chasing an ever-changing animal called process technology advancement that has created issues for us over the last few decades and likely will continue until we reach the limit of physics as we can manipulated them.
Bottom line: love the idealism, but don't buy into this hype with this piddle of investment.