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DARPA Invests $100 Million In a Silicon Compiler (eetimes.com)
The Defense Advanced Research Projects Agency (DARPA) will invest $100 million into two research programs over the next four years to create the equivalent of a silicon compiler aimed at significantly lowering the barriers to design chips. "The two programs are just part of the Electronics Resurgence Initiative (ERI) expected to receive $1.5 billion over the next five years to drive the U.S. electronics industry forward," reports EE Times. "ERI will disclose details of its other programs at an event in Silicon Valley in late July." From the report: Congress recently added $150 million per year to ERI's funding. The initiative, managed by the Defense Advanced Research Projects Agency (DARPA), announced on Monday that the July event will also include workshops to brainstorm ideas for future research programs in five areas ranging from artificial intelligence to photonics. With $100 million in finding, the IDEAS and POSH programs represent "one of the biggest EDA research programs ever," said Andreas Olofsson, who manages the two programs.
Together, they aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs "will change the economics of the industry," enabling companies to design in relatively low-volume chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable, said Olofsson.
Together, they aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs "will change the economics of the industry," enabling companies to design in relatively low-volume chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable, said Olofsson.
I don't think you actually understand how difficult a "silicon compiler" would be to produce. Even relatively known things like FPGA compilers are absurdly complex and rely 99% on arranging tetris block like configurations of flip flops in the tightest configuration possible to avoid wasting space for the given design (and take obscene amounts of time to do so.) Now imagine designing those tetris blocks from the ground up, with variable transistor sizes as tech and manufacturing needs dictate, and breaking the whole thing down at the end into the CNC files to machine out the masks with metadata for the exposure times and it gets mind bogglingly complex. No one guy has a design for even one of those things that is close to comprehensive, let alone all of them. You're talking about things which even broken into their base components would take the life work of several dozen geniuses to achieve if they were in the flow state their entire lives and experts at the specific things they were working on at every level - scale that out to a manageable software development team on a time limit as aggressive as this and 100m is an absolute bargain.
How much of that $500m is legit R&D, and how much is marketing, and how much is payments to partners to use it? How much of it is bogus expenses designed to avoid taxes, and how much of it is actual cash money that walked out the door?
99% of it goes into making masks, configuring equipment, and testing out new designs, so basically all of it. Any kind of development takes iteration to achieve - think of if you had to pay several million dollars every time you hit the debug button on visual studio. That's the equivalent of chip R&D. It takes months of engineers working to craft and machine simple things like masks - on average a mask alone runs a million dollars due to the failure rates in making them and the labor required to do so, and it takes several for the different layers of a chip. Once you've shelled out 10-20m you then have to spend another few million on configuring the equipment to use it and materials which get scrapped in all your calibration fuckups. When all is said and done you're at about 25-30m when you try to debug it. They certainly try to cut costs and find all the possible bugs in that singular debug session, but it doesn't happen, so 4 iterations later if you're lucky you have a new chip at 100m. I'm not actually sure this project will do much if anything to help since the bulk of the cost is in making the things to make the chips (masks, etc) but it seems interesting.
Actually, I've got a ~$20 FPGA dev board on my desk right now, and it isn't going to take me $500m to write a little verilog. ;)
Compilers are hard, but still, they're generally written by a very small software team. The hardware team would not be bigger, if anything it would be smaller.
Do you know how that FPGA compiler works? Chances are it's made by 1 of two companies (the open source cores for FPGAs are terrible) and you've likely noticed it takes around a dozen gigabytes to install the compiler. Now consider that only does arrangements of flip flops and not actual hardware design. Hardware design is like a 2D (and for chips of any complexity, 3D) version of tetris-like compilation. You not only have to compile things in sequence, you also have to make sure they work in parallel and FIT onto a constrained space in the most efficient manner - AND they have to do so without doing things like creating inductive effects which make bits tunnel to the wrong channel of a bus or otherwise screw up calculations - AND you have to take into account heat dissipation - AND you have to take into account the limited external IO pins - AND you have to take into account the limited internal IO pins between those tetris-like blocks - AND you have to take into account changing hardware (how long until you have to scrap the whole compiler and start over because your transistor dimensions changed? 6 months?)
This isn't software design, software is super fucking easy compared to hardware (hint: FPGAs are still effectively software.)
This is actually a project I've read about in the past so I'll explain. What they are trying to do is make a automatic layout engine for silicon. In effect, it will take your VHDL and turn it into a completed layout that is ready for manufacturing. However, to avoid a massive layout times, they also want to be able to use premade layouts for subsystems. If you consider each subsystem to be a block of object code then the layout engine is a compiler that is connecting your "main.c" up to all the functions already compiled.
It's a really good concept but the laws of physics won't make it an easy task and much like handwritten assembly, it's unlikely to be competitive with manual layouts.
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