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DARPA Invests $100 Million In a Silicon Compiler (eetimes.com)

The Defense Advanced Research Projects Agency (DARPA) will invest $100 million into two research programs over the next four years to create the equivalent of a silicon compiler aimed at significantly lowering the barriers to design chips. "The two programs are just part of the Electronics Resurgence Initiative (ERI) expected to receive $1.5 billion over the next five years to drive the U.S. electronics industry forward," reports EE Times. "ERI will disclose details of its other programs at an event in Silicon Valley in late July." From the report: Congress recently added $150 million per year to ERI's funding. The initiative, managed by the Defense Advanced Research Projects Agency (DARPA), announced on Monday that the July event will also include workshops to brainstorm ideas for future research programs in five areas ranging from artificial intelligence to photonics. With $100 million in finding, the IDEAS and POSH programs represent "one of the biggest EDA research programs ever," said Andreas Olofsson, who manages the two programs.

Together, they aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs "will change the economics of the industry," enabling companies to design in relatively low-volume chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable, said Olofsson.

55 of 104 comments (clear)

  1. Geh. by Anonymous Coward · · Score: 1

    That makes sense if you look at the commercial chip design market. The process is error prone and expensive.

    It makes a hell of a lot less sense if you look at some other people busy in the space. Like how Chuck Moore does his chip designs with a "silicon compiler" written by a single person. Meaning that DARPA could have effective chip design tools for as little as a hundred thousand dollars, iff they manage to find the right person to build it for them. Software design is funny like that, and we haven't started to scratch the surface of removing unneccesary complexity, so we're still paying through the nose for most of the software. Usually it's amortised through so many factors and other users that we can pretend to not notice. For one-offs like this... it suddenly becomes glaringly painful just how wasteful software projects tend to be. On top of that, the military-industrial complex is the world's biggest money waster, so this hundred million seems reasonable compared to their other money wasting projects. But it's still wasteful. Even though this is explicitly aimed at reducing costs. I conclude that's just the pretense, and this is really about pork barrels. Funny, eh.

    1. Re:Geh. by Aighearach · · Score: 1

      They don't care about saving a few million dollars if they hire the exact right person, they want to get a good result without having to rely on hiring the exact right person.

      Their goal is to develop partner businesses through the giving of contracts, they're not trying to get the K-Mart Special.

    2. Re:Geh. by NicknameUnavailable · · Score: 5, Interesting

      I don't think you actually understand how difficult a "silicon compiler" would be to produce. Even relatively known things like FPGA compilers are absurdly complex and rely 99% on arranging tetris block like configurations of flip flops in the tightest configuration possible to avoid wasting space for the given design (and take obscene amounts of time to do so.) Now imagine designing those tetris blocks from the ground up, with variable transistor sizes as tech and manufacturing needs dictate, and breaking the whole thing down at the end into the CNC files to machine out the masks with metadata for the exposure times and it gets mind bogglingly complex. No one guy has a design for even one of those things that is close to comprehensive, let alone all of them. You're talking about things which even broken into their base components would take the life work of several dozen geniuses to achieve if they were in the flow state their entire lives and experts at the specific things they were working on at every level - scale that out to a manageable software development team on a time limit as aggressive as this and 100m is an absolute bargain.

    3. Re:Geh. by Anonymous Coward · · Score: 1

      There are existing silicon compilers like VHDL, and those are built up from standard libraries using templates in the same way as C++. Instead of passing class objects, you are passing blocks of bits. Even if you do get the design working and verified, there are still problems with the electromagnetic fields and crosstalk as electrons move around as well as clock timing with all the different parts operating in parallel. So tests have to be done with FPGA's, prototype silicon and then the final chip.

      Large projects go overbudget because they try and do things in parallel or out of sequence simply because the teams are available at the time. So each team has to guess what the interface between the different software/hardware blocks are going to be, then fix the bugs because they didn't get the logic fixed at the time.

    4. Re:Geh. by K.+S.+Kyosuke · · Score: 1

      Red herrings? None of those things actually compute anything. They just allowed a serial state machine to survive longer. They *also* caused the number of transistors to increase disproportionately to increases in performance.

      --
      Ezekiel 23:20
    5. Re:Geh. by ka9dgx · · Score: 1

      You've obviously not heard of the GreenArrays GA144 chip. Insane amounts of compute power in a small passively cooled package.

    6. Re:Geh. by K.+S.+Kyosuke · · Score: 1
      --
      Ezekiel 23:20
    7. Re:Geh. by K.+S.+Kyosuke · · Score: 1

      BTW, your CPUs are postmodern, not modern. Modern CPUs were what you had in the mid-1980s.

      --
      Ezekiel 23:20
    8. Re:Geh. by religionofpeas · · Score: 1

      Insane ? It's got 144 extremely limited cores, with tiny memories, small registers, no floating point, no cache, and no DDR memory interface.

      It's low power, but that's the only good thing.

    9. Re:Geh. by AHuxley · · Score: 1

      Like finding people who could work with Basic and put it on a chip in 1980 difficult?

      --
      Domestic spying is now "Benign Information Gathering"
    10. Re: Geh. by NicknameUnavailable · · Score: 1

      Wrong, the trouble is the task really does require a plethora of geniuses. A genius doesn't live long enough to complete it themselves, and doesn't work fast enough to stay current with technology even if they did live long enough to implement a version compatible with today's hardware designs.

    11. Re:Geh. by NicknameUnavailable · · Score: 1

      No, as in even if you know every aspect of the system from staying current to bleeding edge transistor designs to the logical arrangements of them into cores to the wiring of those cores to the inductive effects between transistors and traces to the other thousand issues which all require special expertise in - you wouldn't live long enough to write it all if you were in the flow state 24/7, started coding on it with expert level knowledge when you were born and lived to 150 years old doing nothing else the entire time. To put this in perspective FPGA cores tend to number in the dozens of gigabytes for a workable implementation - basically a bunch of bitmaps describing the state of flipflops and which of a limited number of neighbor flipflops to connect them to. Actual chip design is billions of times more complex than FPGA design because you're talking about implementing actual transistors and dealing with dead sections of the chip as a matter-of-fact-will-happen-randomly variable and all the other issues described. Look at it this way: what's going to be harder? Drawing a glyph of a house with zero actual spec requirements in MS Paint or etching a photorealistic image of one atom-by-atom into a grain of sand, by hand? That's the equivalent of software vs hardware, the difference is so vast it is absurd to suggest hardware design is anything like software design.

    12. Re:Geh. by mlyle · · Score: 2

      ... Synthesis tools already exist, and every fab has a design library of standard transistors. While the tools are complicated and very expensive (though open source versions exist), they are there. So the problem you're describing is already solved. Designers describe logic, help a little with floorplan and constraints, and get a design out minutes to hours later.

      What's difficult is that we don't have great programming mechanisms to describe parallel logic, or to synthesize sequential descriptions of tasks into efficient sets of gates and transistors. Verilog/VHDL/even SystemC are very, very, very slow and cumbersome to develop in and require a shit-ton of verification. If these could be made even a little more like developing software, it would be a big win.

    13. Re:Geh. by Anonymous Coward · · Score: 1

      Sounds like a job for machine learning and blockchain.

      Quick. Write up a press release.

  2. small budget by religionofpeas · · Score: 1

    In an industry that already spends billions of dollars on design and manufacturing of chips, as per the example of $500 million for a single SoC, what are you going to do with a measly $100 million ?

    1. Re:small budget by Aighearach · · Score: 1

      How much of that $500m is legit R&D, and how much is marketing, and how much is payments to partners to use it? How much of it is bogus expenses designed to avoid taxes, and how much of it is actual cash money that walked out the door?

      So we find out, it doesn't take $500m to make an IC.

      Actually, I've got a ~$20 FPGA dev board on my desk right now, and it isn't going to take me $500m to write a little verilog. ;)

      Compilers are hard, but still, they're generally written by a very small software team. The hardware team would not be bigger, if anything it would be smaller.

      Even individual academics write compilers that work. Even ones who never left the ivory tower can complete the task!

    2. Re: small budget by Anonymous Coward · · Score: 1

      There's a world of difference between coding up an FPGA or the cut and paste IP methodology used in commodity ASIC design, and the processes that went into that Intel CPU or nvidia GPU sitting in your game toaster. The extreme scales and manufacturing means shit goes beyond connecting the dots or even electronic design into serious physics and managing heat and the likes. Your not going to encounter that on your Xilinx hobby board, but it's real and it's expensive with commercial CPU and GPU(etc) design

    3. Re:small budget by ShanghaiBill · · Score: 1

      In an industry that already spends billions of dollars ...

      This isn't about chopping down a bigger tree. It is about sharpening the ax.

      as per the example of $500 million for a single SoC, what are you going to do with a measly $100 million ?

      Make future SoC designs cost a lot less.

    4. Re:small budget by religionofpeas · · Score: 1

      If a $100 million effort can make a $500 million SoC design cost "a lot less", then these projects would already have been done.

    5. Re:small budget by religionofpeas · · Score: 2

      Compilers are hard, but still, they're generally written by a very small software team.

      Compilers for hardware targets are a lot harder than for a general purpose CPU, because the hardware offers much more degrees of freedom in implementing a design.

    6. Re:small budget by NicknameUnavailable · · Score: 5, Interesting

      How much of that $500m is legit R&D, and how much is marketing, and how much is payments to partners to use it? How much of it is bogus expenses designed to avoid taxes, and how much of it is actual cash money that walked out the door?

      99% of it goes into making masks, configuring equipment, and testing out new designs, so basically all of it. Any kind of development takes iteration to achieve - think of if you had to pay several million dollars every time you hit the debug button on visual studio. That's the equivalent of chip R&D. It takes months of engineers working to craft and machine simple things like masks - on average a mask alone runs a million dollars due to the failure rates in making them and the labor required to do so, and it takes several for the different layers of a chip. Once you've shelled out 10-20m you then have to spend another few million on configuring the equipment to use it and materials which get scrapped in all your calibration fuckups. When all is said and done you're at about 25-30m when you try to debug it. They certainly try to cut costs and find all the possible bugs in that singular debug session, but it doesn't happen, so 4 iterations later if you're lucky you have a new chip at 100m. I'm not actually sure this project will do much if anything to help since the bulk of the cost is in making the things to make the chips (masks, etc) but it seems interesting.

      Actually, I've got a ~$20 FPGA dev board on my desk right now, and it isn't going to take me $500m to write a little verilog. ;)
      Compilers are hard, but still, they're generally written by a very small software team. The hardware team would not be bigger, if anything it would be smaller.

      Do you know how that FPGA compiler works? Chances are it's made by 1 of two companies (the open source cores for FPGAs are terrible) and you've likely noticed it takes around a dozen gigabytes to install the compiler. Now consider that only does arrangements of flip flops and not actual hardware design. Hardware design is like a 2D (and for chips of any complexity, 3D) version of tetris-like compilation. You not only have to compile things in sequence, you also have to make sure they work in parallel and FIT onto a constrained space in the most efficient manner - AND they have to do so without doing things like creating inductive effects which make bits tunnel to the wrong channel of a bus or otherwise screw up calculations - AND you have to take into account heat dissipation - AND you have to take into account the limited external IO pins - AND you have to take into account the limited internal IO pins between those tetris-like blocks - AND you have to take into account changing hardware (how long until you have to scrap the whole compiler and start over because your transistor dimensions changed? 6 months?)

      This isn't software design, software is super fucking easy compared to hardware (hint: FPGAs are still effectively software.)

    7. Re:small budget by K.+S.+Kyosuke · · Score: 1

      By the companies selling the multi-gigabyte software tools? Oh, my sweet summer child...

      --
      Ezekiel 23:20
    8. Re:small budget by religionofpeas · · Score: 1

      Why not ? Make better tools, charge more money for them.

    9. Re: small budget by drinkypoo · · Score: 1

      Let's see how you design software, which is essentially solving a rubiks cube with an unspecified, potentially infinite, number of dimensions. Hardware is a joke.

      In hardware you have to fit everything into just two dimensions. In software you have an infinite number of dimensions available, and thus you can fit an infinite amount of complexity into the job without even thinking where it goes. It's obvious that this makes developing software simpler than developing hardware.

      --
      "You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
    10. Re: small budget by mnemotronic · · Score: 1

      No[. H]ardware is harder due to having to deal with physical reality, and getting less chances to fix

      That "physical reality" bit is correct but IMHO really glosses over the vast number of physical limitations and constraints that hardware has to deal with. Beyond the electrical design there's the physical layout (real-estate) kingdom. Limitations in layout, or any of the following, sometimes require changes to the electrical design which then modifies the layout. This loop can repeat.

      • * Power consumption limitations
      • * Voltage and ground routing
      • * RF constraints
      • * Timing constraints
      • * Providing for embedded testing

      Then there's the material physics and chemistry required for fabbing the freaking thing.

      Considering that this tool could be used by the various gov't TLA agencies, physical security features of the device may be a requirement, like features to prevent or forestall reverse engineering or obscure algorithms implemented in the circuitry.

      I think if software had similar constraints, a program would have to be written in assembly language, SQL, APL and Javascript, all combined and interspersed in the same file, where each language would be restricted to a different subset of alphanumeric characters. Code would have to be written in rows and columns. "If" statements would not allowed to be near looping constructs.

      --
      The Russians have won. They have made the world a cesspool of distrust, greed, fear and hate.
    11. Re: small budget by NicknameUnavailable · · Score: 1

      A software compiler translates abstract ideas which have been carefully fine-tuned by hand into machine code of a VERY simple kind - based on the spec of the chip it is written for. Both systems are arbitrarily complex, the differences are primarily that the software developer can "debug" without blowing tens of millions of dollars each time they press the button (try writing a complex million-line system without hitting the debug button until it's "done" - then catching every error you can and doing it again as few times as possible - to the point of taking months between each debug session just to check the data you got from the last one.) Your comment is a joke.

  3. Re:Clawing back electronics manufacturing by ShanghaiBill · · Score: 2

    It's about time that such a strategic industry gets revived.

    Chip design is dominated by America. There is no need to "revive" it.

    Chip manufacturing will still be done in Asia.

  4. This is DARPA, so specialised chips by AntisocialNetworker · · Score: 2

    DARPA have different requirements for chips than the rest of us. For example, they might not want separate "systems management" circuits.

  5. Not a compiler, a layout engine by Gravis+Zero · · Score: 3, Interesting

    This is actually a project I've read about in the past so I'll explain. What they are trying to do is make a automatic layout engine for silicon. In effect, it will take your VHDL and turn it into a completed layout that is ready for manufacturing. However, to avoid a massive layout times, they also want to be able to use premade layouts for subsystems. If you consider each subsystem to be a block of object code then the layout engine is a compiler that is connecting your "main.c" up to all the functions already compiled.

    It's a really good concept but the laws of physics won't make it an easy task and much like handwritten assembly, it's unlikely to be competitive with manual layouts.

    --
    Anons need not reply. Questions end with a question mark.
    1. Re:Not a compiler, a layout engine by religionofpeas · · Score: 1

      Sounds like an area where machine learning could help in the near future. You know the goals, and you can run design through simulations to see how close you get to the goal.

    2. Re:Not a compiler, a layout engine by EETech1 · · Score: 1

      Because anybody can use Simulink!

    3. Re:Not a compiler, a layout engine by AHuxley · · Score: 1

      A gov CPU that does Ada really quick?

      --
      Domestic spying is now "Benign Information Gathering"
    4. Re:Not a compiler, a layout engine by smallfries · · Score: 1

      It will be competitive, but only on different metrics. Manual layout will win on size, performance, power efficiency etc, but the new approach will end up winning on design time. This has a larger effect on product cost and time to market for applications they are targetting.

      --
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    5. Re:Not a compiler, a layout engine by Gravis+Zero · · Score: 1

      yeah, that the whole "much like handwritten assembly" part, duh. -_-

      --
      Anons need not reply. Questions end with a question mark.
    6. Re:Not a compiler, a layout engine by smallfries · · Score: 1

      I was not agreeing with you as you seem to assume - read it again. Duh

      --
      Slashdot: where don knuth is an idiot because he cant grasp the awesome power of php
  6. What does it do? by DeAxes · · Score: 2

    I've been trying to understand what this actually does and after reading the article I still don't understand it!
    The name Silicon Compiler is confusing beyond belief; traditional compilers convert programming languages to assembly, so a Silicon Compiler seams like it would convert different assembly languages, so code would run no matter the architecture.
    The article seems to mention new ways to wire the different architectures, making me think it's a computer aided architecture design using AI, but then mentioned open sourcing the architecture design.
    So I come back to you: What the hell does this "Silicon Compiler" actually do?

    1. Re:What does it do? by AHuxley · · Score: 1

      Like the computers in the 1980's that shipped with Basic on a chip. Turn the computer on and trust the chip to make the correct code.

      --
      Domestic spying is now "Benign Information Gathering"
    2. Re:What does it do? by mikael · · Score: 1

      You can convert a software algorithm in a high level language into a silicon compiler language like Verilog or VHDL. These support variable types like floating point and variable sized integers. But everything is done using bits. Each function takes in inputs as sets of bits, and outputs as sets of bits along with a clock signal. The silicon compiler will convert this code into a series of logic blocks. Variables become hardware registers. Conditional statement become AND, OR and NOT logic gates. Maths libraries will become transistor logic and lookup tables. Presupplied templates provide optimized transistor logic for arbitrary sized integer arithmetic like multiplication and division, video compression and so on. Many other libraries will already have been precompiled and optimized for side/speed) that are connected together. Using tiling algorithms these logic blocks are arranged into the tightest space taking into account power and clock lines.

      --
      Vintage computer adverts: http://www.vintageadbrowser.com/computers-and-software-ads
    3. Re:What does it do? by angel'o'sphere · · Score: 1

      Obviously it compiled a high level language, looking like Ada or VHDL, into production masks to create a chip or SoC (made from silicon) on a wafer.
      Hand in your geek card.

      --
      Cost free eBook I read (by iBook/Kobo/Amazon/ObookO/Gutenberg etc.): "The Green Odyssey" by Philip Jose Farmer.
    4. Re:What does it do? by religionofpeas · · Score: 1

      Except these things already exist, and chips are still really expensive to make.

    5. Re:What does it do? by angel'o'sphere · · Score: 1

      Of couese they exist. But a government funded 'restart' might yield quicker better results than waiting for improvement of the existing tools.

      --
      Cost free eBook I read (by iBook/Kobo/Amazon/ObookO/Gutenberg etc.): "The Green Odyssey" by Philip Jose Farmer.
    6. Re:What does it do? by DeAxes · · Score: 2

      Thanks for telling me it's OBVIOUSLY, given the name, a hardware based software compiler, which automatically compiles it on the fly using it's own hardware.. If you said that to me, you would be completely WRONG. Not only is that already in existence, it's very costly and often has no real benefit for the expense.
      From the article: "Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards."
      So, the article says it's a library of Open Source SoC designs and a layout tool to put these SoC's together.
      While I think the layout tool is interesting, it's going to be hard to get traction on the open sourced design elements.

  7. Companies do not invest in the long term by bussdriver · · Score: 1

    Most the innovation does not come from manufacturing. Big risk is what pure research does; some of it seems completely pointless at the time it is being done-- the applications of the gained knowledge are unknown at the time; furthermore, many things are discovered by accident.
    This is $$$ put into "future work" areas that companies have little incentive to explore; especially companies on the market who are always under pressure to cut R&D for greater returns for investors.

  8. Only $100M? Nowhere near enough, DARPA... by StandardCell · · Score: 5, Insightful

    As a former lead ASIC designer, I can say this is one of the most ambitious projects likely ever undertaken in EDA. Companies like Cadence, Mentor and Synopsys have been working on these problems for literally decades now. Everyone wants an easy solution for push-button design, but it is hardly that simple. Consider the following:

    - Synthesis from RTL-to-gate level
    - Functional design rule checks
    - Place and route, including clock routing, PLLs/DLLs, etc.
    - Timing extraction and static timing analysis
    - I/O/SSO and core power
    - Internal signal integrity and re-layout
    - Test insertion and test vector generation
    - Formal verification
    - Functional verification
    - Packaging and ball-out/bonding, especially with core I/O
    - Physical design rule checks / Netlist vs. layout checks

    A suite of tools that does all of this costs into the millions of dollars today, and is really a subscription as there are always bugs and improvements to be made. It also assumes physical design rule decks from the silicon vendors that have gone extensive characterization on limits such as minimum feature widths and notch rules can yield to a sufficient level economically, and that the gate and hard IP/mixed IP libraries have been validated. Front end functional design often requires re-architecture due to considerations when physically implementing the chip. All of this, of course, presumes that we don't run into additional phenomena that were irrelevant at larger process nodes (e.g. at ~250nm/180nm, wire delay dominated gate delay, and at 90nm/65nm, RC signal integrity models gave way to RLC, plus power/clock gating, multi-gate finFETs vs. single-gate planar past 22nm, etc.).

    A push-button tool would have to take all of this into consideration. But let's face it...as well-intended as this is, you probably need another couple of orders of magnitude of money thrown at this to even begin succeeding under the fundamental assumption you don't have additional phenomena like alternatives to manufacturing. And that's the fundamental catch that is not captured in the article: we are chasing an ever-changing animal called process technology advancement that has created issues for us over the last few decades and likely will continue until we reach the limit of physics as we can manipulated them.

    Bottom line: love the idealism, but don't buy into this hype with this piddle of investment.

  9. Re:100 Millions by PPH · · Score: 1

    99 million for patent lawsuits.

    DARPA, working on government applications. Patents do not matter.

    --
    Have gnu, will travel.
  10. Re:Clawing back electronics manufacturing by alvinrod · · Score: 1

    There are still a lot of chip fabs in the U.S., but even if the wafers and dies are made in the U.S., they're going to be shipped overseas for assembly into the final product.

  11. Re:Clawing back electronics manufacturing by AmiMoJo · · Score: 1

    The US does need to keep innovating like this to stay ahead though. China is producing some really competitive chips now, especially for mobile devices (CPUs, cellular modems).

    --
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    SJW, n: "Someone I don't like, and by the way I'm a fuckwit" - AC
  12. Re:Clawing back electronics manufacturing by alvinrod · · Score: 1

    Other parts of the package are made overseas due to costs, so it's a matter of shipping more components to the U.S. to assemble the final product and then having to ship that back to Asia again anyways as most computers or other devices (phones, tablets, routers, etc.) are assembled there as well. Add in less expensive labor costs in Asia (and no one wanting to make a large capital investment into robotic assembly lines if they don't have to) and it just makes more sense to finish the assembly in Asia.

  13. Re:Clawing back electronics manufacturing by ChatHuant · · Score: 1

    he US does need to keep innovating like this to stay ahead though. China is producing some really competitive chips now, especially for mobile devices (CPUs, cellular modems).

    It seems very shortsighted for me that the USA has put itself in this situation - because this is a great scenario for China, not so much for he USA. When the USA keeps innovating and China immediately takes the innovation (for example, via laws that force American companies to relinquish the intellectual property, or via straightforward theft) and mass produces it, the money and power go to China. In this pairing, the USA is the weak partner; if China blocks the production of new USA designs, the USA has nothing - and it would take years or tens of years to develop elsewhere a production capacity that could replace China's. If it's the USA that stops providing new designs to China, China will just innovate more slowly, using local research and development; in the meantime it can keep producing and selling products at the current technological level, while the USA is again left with nothing.

    Being the producer of stuff means you get paid again and again for the stuff you produce. Being the inventor means being paid maybe once. After you disclose your invention, the producer doesn't need to pay you anymore - unless there is some kind of legal infrastructure, like IP laws, that protect you - but we know how well this works with China.

  14. "DARPA Hard" by Required+Snark · · Score: 2
    This is what DARPA is supposed to do: tackle problems that are too risky for private funding. The phrase for it is "DARPA Hard".

    They often get a lot of bang for the buck because they attract more investment from partners in both academic research and business. That is what the DARPA Grand Challenge projects are all about. Remember the autonomous vehicle race from California to Las Vegas? Or the emergency rescue robot competition? Things like that.

    In fact, both of those were "failures". The goals were not met. The robots fell over. No team finished the Mojave race. The prizes were not awarded. But the government got more then it's money's worth. And everyone who participated learned a whole lot. For DARPA that was a good result.

    So stop whining about the futility of the project just because you are too short sighted to understand what it is really about. There are plenty of very very smart motivated people who do get it, and they are going to produce some very interesting work. Go back to computer and watch someone else play a video game. It's all you're good for.

    --
    Why is Snark Required?
  15. Re:Why? by AHuxley · · Score: 1

    Private industry still trusts its software and the people who code.
    The US mil cannot even trust its most secure systems and the contractors that make the new code.
    Too many people from outside the USA, cults, faith groups, contractors with split loyalties, contractors open to blackmail are now wondering around very secure projects.
    In the past the project would secure the contractors and get to work.
    Due to the way contractors are now hired everyone can be security risk and still get a gov/mil job.
    The kind of project thats only needed when everything cannot be trusted and once trusted complier problems are now presenting in all other US projects.

    --
    Domestic spying is now "Benign Information Gathering"
  16. Re: Why? by Reverend+Green · · Score: 1

    Funny thing: I'm a pot-smoking communist sympathizer who thinks national hero Edward Snowden deserves the Medal of Freedom. So I'm pretty sure I would never get a clearance.

    But there's no fucking way I would ever sell out my country. No amount of money or blackmail would make me put a back door or other bug in a sensitive military system. Even when I hate my government I still love my country.

    So my question is, where the fuck are they getting these contractors? People who somehow DO qualify for a clearance. But are still gonna sell us up the river to the Chinese (or whoever)?

  17. Re: Why? by AHuxley · · Score: 1

    Think of it in terms of a not using the question of a failed clearance not to hire a person anymore.
    A person is not considered on their security risk rather on their ability to make the gov be like the wider US community.
    Merit, skill, the question of security, education cannot be used to stop a contractor from getting hired.
    Criminals can now ask to work for a government/mil.
    People with not real history in the USA get to work on the most sensitive projects.
    Contractors can set up a front company with a lawyer, former mil/gov person and a few cleared workers.
    As long as they sort the paperwork, anyone can do the contract work globally. That makes the price a bit lower than a real company in the USA.
    Do that for a decade and the US gov/mil starts to take in a lot of people who cant be trusted.
    A bit like the UK mil/gov did in the 1920-50's. Spies fill the career fairs and too many get in. A quick look over digital criminal state and federal records by a contractors at very best. No search over a persons life, education, politics, friends, family, connections to the USA, university politics.

    Re "But are still gonna sell us up the river to the .... "
    Spy networks work in a few ways in the USA.
    The new instant friend who is perfect and wonderful.
    Direct blackmail on a hidden secret.
    The search of all past US security clearances by other nations as they now have the files copied. The split loyalty question as a cult, faith, another nations/faith asks a person to give away secrets.
    Using a cult, faith group, political group to pass in decades of resumes and get as many people in for later decades in the US government.
    That was an East German method. Get as many new graduates in to the West and advance up the ranks over the decades.
    No contact or links back and nothing could be tracked. A holiday years later would be the setting to go over results.
    A person is an addict, has cash problems, wants more wealth and someone new makes an offer.

    The way the US countered that was the long chat down during the polygraph "interview".
    All the history of a persons banking, education, politics, spending, friends, addictions, lifestyle was investigated before the interview and then the person was guided to talk about security aspects of their past. All that detail ended up in a digital file.
    Such methods then only allow the best of the best in and the US gov/mil starts to be very different from the wider US demographics.
    The other test is 2 FBI with accents show up for a chat down and offer cash and a hint that they know about a persons life.
    Is that contact reported in detail? Is the cash accepted?
    So many random people now have US security clearances the FBI cant keep track.

    The only way the USA can counter the spy and faith problem is with more AI, computers, the buddy system and security.
    The buddy system says the person working with another person can never be be trusted. As the team size gets larger thats a total lack of trust.
    The trust in compilers for gov/mil software is now gone too. Should have hired on merit and only after accepting real security clearances.

    The better news is that can all be fixed. Just do what the UK did in the 1970's and security can be restored within a generation.
    Good pay and real advancement on merit. Education and knowing everyone has a real security clearance.
    The UK ensured a esprit de corp into the 1990's. The US now has the buddy system so everyone is stressed with who they have to work with.
    That stress results in lifestyle changes, addictions, deviancies, blackmail, finding "faith" in a cult. Spies wait off base/port/fort/camp ready to be supportive as a new best friend.

    --
    Domestic spying is now "Benign Information Gathering"
  18. Re:Clawing back electronics manufacturing by Highdude702 · · Score: 1

    Actually AMD already ships the silicon chips to either NY or FL to be packaged. Idk about intel.

  19. Re:Clawing back electronics manufacturing by stoatwblr · · Score: 1

    Labour costs aren't much cheaper in asia. The win is in logistics.