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DARPA Has an Ambitious $1.5 Billion Plan To Reinvent Electronics (technologyreview.com)
The Defense Advanced Research Projects Agency (DARPA), which funds a range of blue-sky research efforts relevant to the US military, last year launched a $1.5 billion, five-year program known as the Electronics Resurgence Initiative (ERI) to support work on advances in chip technology. It has now unveiled the first set of research teams selected to explore unproven but potentially powerful approaches that could revolutionize US chip development and manufacturing. From a report: The ERI's budget represents around a fourfold increase in DARPA's typical annual spending on hardware. Initial projects reflect the initiative's three broad areas of focus: chip design, architecture, and materials and integration. One project aims to radically reduce the time it takes to create a new chip design, from years or months to just a day, by automating the process with machine learning and other tools so that even relatively inexperienced users can create high-quality designs.
"No one yet knows how to get a new chip design completed in 24 hours safely without human intervention," says Andrew Kahng of the University of California, San Diego, who's leading one of the teams involved. "This is a fundamentally new approach we're developing." William Chappell, the head of the DARPA office that manages the ERI program, said, "We're trying to engineer the craft brewing revolution in electronics." The agency hopes that the automated design tools will inspire smaller companies without the resources of giant chip makers, just as specialized brewers in the US have innovated alongside the beer industry's giants.
"No one yet knows how to get a new chip design completed in 24 hours safely without human intervention," says Andrew Kahng of the University of California, San Diego, who's leading one of the teams involved. "This is a fundamentally new approach we're developing." William Chappell, the head of the DARPA office that manages the ERI program, said, "We're trying to engineer the craft brewing revolution in electronics." The agency hopes that the automated design tools will inspire smaller companies without the resources of giant chip makers, just as specialized brewers in the US have innovated alongside the beer industry's giants.
eliminating the thousands or tens of thousands of timing violations. ASIC development goes a compilation process of source code not entirely different than software. The challenge of ASIC design is locating everything just right so that distance is globally nearly-minimized (local optima but near the global optimum) to get all the electron pulses to arrive where they need to arrive before it is too late. Plus, each logic gate costs a time delay (as well as occupies space exacerbating the distance problem). So another trick to solve timing violations is to simplify the design is some locality to lessen the depth of gates that a signal/calculation/operation must traverse, when viewed as a directed-acyclic graph (DAG). Sometimes space (# of gates) can be bloated up to decrease the depth of the walks of the logic-gate DAG (but then that increases area on the die, which exacerbates the distance problem).
If you're going to do an Archer-style quote, at least do it properly:
"Do you want Skynet? Because that's how you get Skynet."
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AMD seems to be doing just fine with 7nm, so not sure how Intel sitting on their hands relates to this.