Samsung Chips Will Get Faster and Easier on Your Battery in 2020 (cnet.com)

Processor progress is harder to come by these days, but Samsung says it'll build chips next year that will give you a bit more battery life or a little more speed. From a report: Through improvements charted by Moore's Law, chip electronic components called transistors get steadily smaller. On Monday, Samsung said it's taken the next step along the Moore's Law path, shrinking a transistor measurement to 5 billionths of a meter -- 5nm -- from 7nm. To get some idea of just how teensy that is, about 2,000 would fit end to end across the width of a human hair. The new petite size means the Korean company will be able to add more electronic abilities to its chips. It also means the chips will get either a 10% speed boost or a 20% savings in power. The development could help not only Samsung, which builds the Exynos processor for its own phones, but also Qualcomm and other companies that rely on Samsung's foundry business to build their chips.

Comments

The problem isn't the CPU

[EmagGeek]

The problem isn't the CPU. The problem is all the Apps that insist on running constantly in the background, using GPS and other tracking sensors to spy on you.

I have a Moto G4 and I couldn't figure out why the battery was only lasting 6-8 hours. One day I finally quit Facebook and uninstalled the Apps for Facebook and Messenger, and voila! Now I get 24+ hours of battery life easily.

Get app developers under control and you get battery usage under control.

5nm is NOT a true process

[Anonymous Coward]

5nm, of course, is just a tweak of the 7nm process- where only certain chip elements have the smaller size. The power and or clock improvements are real.

Samsung competes with TSMC, which has its 7mn+ process coming later this year to same effect.

The real story is not this nonsense, but the issue of EUV (use of ultra-violet wavelengths with masks) and possibly larger wafers. Both these techs have been delayed for a decade now, cos of fundamental issues. Intel has crashed and burnt over both, having now the WORST process tech amongst the giants.

EUV is currently used as little as possible, and only on layers where trad wavelengths can no longer be forced to give improvements. No fab has proven the feasibility of going full UV, even after 15 years of research in this area by the tool makers.

Current 7nm has two tweaks available for minor improvement- and this article talks of one of these tweaks. After both tweaks have been rolled out, a wholly new process is going to prove to be insanely expensive and difficult, and is probably FIVE to ten years out.

AMD's answer is CHIPLETS- lots of smaller chips sitting on the same substrate- so a 'chip' is improved by using more chiplets. AMD's new Zen2/Ryzen 3 release in a few months time is a chiplet design, where 4 chiplets (CPU or GPU clusters) can sit around the same I/O chiplet.

PS as process shrinks finally end (we don't know how many more we have left, but they will have exponentially longer gaps between each new process to come), there is another option. Circuit improvement. Current circuits are usually sub-optimal, being cheaply placed by very poor chip CAD software that is designed to make the chip design process EASY, not good or efficient.

By allowing far better CAD algorithms, of Human input from 1st class Human circuit designers, a current process could probably see a 2-5 times improvement in many areas. With a tweaked 7nm being around for maybe as long as 10+ years in the worst outcome, there is loads of opportunity for superior circuit design to provide significant improvements (the very reason Apple now designs its own chips).

Re:5nm is NOT a true process

[thegarbz]

By allowing far better CAD algorithms, of Human input from 1st class Human circuit designers, a current process could probably see a 2-5 times improvement in many areas. With a tweaked 7nm being around for maybe as long as 10+ years in the worst outcome, there is loads of opportunity for superior circuit design to provide significant improvements (the very reason Apple now designs its own chips).

I call bullshit on this last part. If there was a 2-5x speed improvement to be had by optimising by human experts we would be having those. I mean how many experts in the world would we need? There's only a few major players in this market and I guarantee you they aren't mashing the autoroute key and calling it a day.

Marketing and manufacturing capability..

[willy_me]

The quoted manufacturing capability is no longer accurate. It is now artificial. Back in the day, a 65nm process was indicative of a manufacturing process that could create features with a minimum pitch of 65nm. Then people started to create FinFET transistors - a process that allows for denser transistors. But how to sell such a process? The answer is to call it a 0.6*65nm process -- when it is actually still a 65nm process. The idea is that the new FinFET transistors result in the same transistor density that would have been achieved with traditional transistors and a 0.6*65nm process.

So the quoted pitch is now an indicator of transistor density -- sort of. Marketing also has a say so one should not read too much into it. Smaller is better but only for the same fab. It is not a good metric for comparison between fabs.

NOTE: The 65nm and 0.6 numbers are just for this example. Actual values will differ. I believe 14nm parts use a 22nm process - but one should verify if you want exact numbers.

Re:Marketing and manufacturing capability..

[SemiChemE]

Your description isn't terribly accurate either. Back in the days of planar semiconductors, the process node (eg. 45nm, 32nm, 22nm) referred to the minimum feature size, which was also at least approximately the minimum gate length. There are other features, particularly some metal line widths in the Back End Of Line (BEOL) that were also close to the nominal node size. The problem in modern technology is that as you scale down the gate length, short-channel effects, particularly Drain Induced Barrier Lowering (DIBL) begins to dominate. This effect degrades transistor performance, such that it is no longer practical to scale gate lengths much below ~20nm. We could easily print 7nm gates, but the resulting devices would be power hungry, hot and slow, not exactly the combination anybody wants!

Now having said that, some gate scaling is still possible, but whereas in the past, gates were routinely scaled by ~30% between each node, today gate scaling is on the order of a few percent and even that requires a lot of work to optimize the device junctions, so as to constrain DIBL. Nevertheless, there are still gains to be had by scaling other aspects of the device. Moving to Finfets, where the gate wraps around a "fin" of silicon provides two advantages. First, the fin itself has a vertical dimension, which corresponds roughly to the width of conventional planar device. This means that if we want more current per unit area, instead of widening the transistor, we can make the fin taller (within limits). So, we are kind of scrunching the transistors into a smaller space. The other and perhaps more important advantage is that because the gate wraps around a very thin fin of silicon, it has better control of the silicon channel, reducing DIBL and other short channel effects. Thus, thinning down the fin provides not only a density benefit, but also a performance benefit.

In today's technology nodes, the smallest dimensions no longer correspond to the gate length, but they do correspond roughly to the fin size. As far as I'm aware, all of today's 7nm processes consist of Fins in the 6-9nm range. I believe there are also some metal lines that are of similar size, which helps in providing more flexibility in routing the connections between various circuits.

Finally, regarding comparing technologies between fabs, the comparison is somewhat complicated by some specific design choices about the basic SRAM and Logic cells and how they are allowed to be connected. In particular, Intel's 10nm process, uses a very aggressive BEOL. This allows them to make small cells of comparable density to the 7nm process of Samsung and TSMC. By contrast, Samsung and TSMC have a relaxed BEOL, so they sacrifice some density, but retain a lead in the raw transistor performance. The end result is that intel's 10nm process and 7nm processes of their competitors are all very comparable.