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A $1000 Supercomputer?

Sean Mooney writes "CNN is reporting that $1000 pc that is 60,000 times faster than a PII 350 may be on the market within 18 months. Star Bridge Systems is making the field programmable gate array (FPGA) computer. These are the same guys who are making HAL, reported earlier. " I'll believe that when I see it. Although I can't think of a better way to break Moore's Law.

2 of 143 comments (clear)

  1. Massive parallelism - still a long way to go by Chilli · · Score: 4
    The problem with the type of calculation that they use to predict the performance of the machine is that, given todays state of the art in parallel computing, a machine with a million processors doing 10 operations per second is not the same as 10 processors doing a million operations per second each.

    Your average C program has very little implicit parallelism (= parallelism not explicitly introduced by using some library of parallel operations or so). Even the best compilers on this planet won't make these programs run much faster on a massively parallel computer than on a single processor (on the contrary, the additional communication overhead can easily make the execution slower with each processor that you add).

    Remember what a fuzz it has been to make the Linux kernel perform well on SMPs with more than two or three processors; how do you want to make this scale to tousands and millions of parallel processing units? BTW, the last company that went for many small (and slow) processing units instead of a few very fast ones was Thinking Machines (the machine was called CM-2). Do a search on the Web to see where they are now...

    Chilli

    PS: Such a machine can be useful for some things, called embarrassingly parallel problems/algorithms in the parallel computing community.

    --
    -=- Just a random lambda hacker
  2. Lies, damned lies and statistics... by substrate · · Score: 5

    or performance claims in this case. Notice that for the performance they compare the IBM Pacific Blue running real code to their machine doing a 4 bit adder. The reason for this provides insight into the technology they're using.

    Their computer is based around FPGAs (Field Programable Gate Arrays), in particular they are using the XILINX family of FPGA. These are devices that are composed of thousands of small logic blocks wired together through a switching network. The functionality of these small logic devices is user definable by setting bits in an SRAM. The connectivity between pins and the logic blocks and other logic blocks is also user definable by setting bits in static RAM.

    So what they're doing is setting each of these programmable blocks to implement a 4 bit adder and wiring them together such that they're all operating at once. It isn't actually doing any useful calculation. There performance claim is based on wiring together a bunch of useless logic and running it all in parallel. Once you start doing useful things the amount of parallelism will reduce. It'll reduce a lot. FPGA's aren't very fast devices, they'll only get a few percentage points (if that) of their performance claim for real applications.

    Porting code to this machine would be non-trivial as well. Rather than the normal programming languages computer scientists and programmers are familiar with you're actually controlling the flow of electrical signals. They've probably got synthesis tools that will take some variant of a program language and translate it into the native data needed to program the device. The synthesis tools are most likely very crude and to get real performance you'd probably have to hack bits. Not fun. I say this because of my experience with synthesis tools used for ASIC design. They're fine if you're doing boring design of maybe 50 or 100 MHz. Beyond that you're pushing there technology and it will probably break. These synthesis tools are designed by billion dollar companies. It would take massive amounts of man hours and money to create a well designed synthesis package for something of this magnitude.