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Bell Labs claims to have found new limit for chip size
Nocturna writes "SiliconValley.com reports scientists at Bell Labs claim to have found a new limit on how small they can make chips, doubling the life left in silicon technology. " Essentially, what Bell Labs is saying that you can't go any smaller then 5 atoms of silicon dioxide at the heart of the machine. As before, they are saying that this the limit-although this time it may veryw ell be true, with current materials.
When current flows through a wire, atoms in the wire tend to be dragged along with the current. The current density - current per unit cross-sectional area of the wire - has to be kept below safe limits (dependent on temperature) to prevent this. Faster chips are made by passing the same amount of current through smaller transistors - but this means through smaller wires, too. Electromigration limits how small you can shrink the wires before your chip dies an early death. Copper helps - it is much more resistant to electromigration than aluminum - but it's still a big problem, and will keep getting bigger.
You get capacitive coupling between wires that are close together - signal leaks from one to the other. This is worse for wires that are closer together, and worse for higher frequencies. As chips shrink and are clocked more quickly, capacitive coupling becomes an ever-greater problem. Capacitive coupling also causes signal leakage between the various parts of a transistor, as well as between transistor sources/drains and the substrate (though silicon-on-insulator helps eliminate this last effect).
A chip's total parasitic capacitance doesn't depend that much on the size of its transistors; just on its total area. Charging and discharging this capacitance dissipates a certain amount of energy (dependent on the chip voltage). As chips are clocked more quickly, power dissipation goes up in proportion to the clock speed. Reducing the core voltage helps a bit, but the core voltage must always be considerably higher than the transistor threshold voltage. Silicon-on-insulator lowers the total parasitic capacitance, but only to a certain point. The problem remains.
This list completely ignores fabrication difficulties at finer linewidths, though those look like they're tractable. However, electrical problems will still pose limits to how small you can shrink features on a chip. When exactly these limits will come into play remains to be seen, but they are lurking.
IMO, most likely better use of silicon at a fixed feature size. You can improve performance by making transistors with a lower threshold voltage (with better-doped silicon or by using another material). You can also boost performance by tweaking the materials used to reduce parasitic capacitance. You could also start developing true multi-layer chips that have more than one layer of transistors, to keep ramping up density (though cost per transistor will level off very quickly and stay constant). More work could also be put into cooling systems that let you clock chips more quickly without having to worry about electromigration. Several other optimizations are probably possible.
Basically, what will happen is that integrated circuits will become a mature technology. Right now they're still in their rapid development stage (think of it as a really long adolesence
That would almost certainly be impractical, as your computing device would have to be kept extremely cold (cold enough to make liquid helium look hot).
There are two obstacles that I can think of. The first is heat disspiation; heat will have to travel farther through the chip before reaching the surface. This could be ameliorated by putting sheets of thermally conducting material between layers, but this is complicated, and they'd have to be pretty thick (unless they were thermal superconductors; IIRC these exist at room temperature).
The other obstacle is depositing a layer of crystalline silicon to make transistors with. Current wafers are still sliced from single crystals of silicon. However, silicon that is deposited tends to be polycrystalline. This gives it poor electrical properties.
We'd either have to figure out how to grow or place single-crystal layers of silicon on to an outer oxide layer of a chip, or else figure out how to make fast circuitry with polycrystalline silicon.
That having been said, this is an idea that I like very much. It is one of the logical ways of extending chips once linewidth reaches its limits.
http://www.bell-labs.com/news/199 9/june/24/1.html
For more info, of course...
That must mean my house is very low power - it only has 60 Hz of power! How will I be able to power one of these chips if my house doesn't have enough power?
Opticom is a Norwegian based company developing unique all-organic and hybrid silicon/organic memory. They have a working prototype of a 1 Gb 62ns ROM chip. They use a hybrid design combining silicon driver circuitry and Opticoms ROM film. The ROM chips demonstrated the feasibility of multiple memory layers (2-6 layers).
I've seen lectures demonstrating solutions for many of the heat issues. At the University of Utah there are research projects (with a bunch of funding from Intel and IBM, where the results are being targetted at production) which tackle the issue of how to use fully asynchronous circuits within a standard CPU, and how to eliminate the refresh of the entire CPU on each clock cycle.
This does indeed help - however, not that much on a well-designed chip.
A lot of the focus of chip optimization nowadays has been on improving scheduling techniques to let programs take full advantage of all of the chip's facilities at any given time. The eventual goal is that if the chip has two FPUs and three integer arithmetic units, it will be performing two FP calculations and three integer calculations per clock, with no units sitting idle. Asynchronous chips give you a large power savings when you _do_ have chip components sitting idle - you are no longer clocking a module that isn't being used. However, for a chip that is using all parts of itself, all components _have_ to be clocked, which limits the savings that you get from making a chip asynchronous.
It's still a worthwhile optimization; it just won't save you from heat problems as clock speeds rise.
Yes, it does. At the suggestion of another slashdot reader, I did more research on electromigration, and it actually has a very strong dependence on temperature.
Cooling computers to very low temperatures does solve or at least help a lot of problems, but is impractical for many applications. Heat flow problems will also be significant for chips that generate a lot of heat in very small areas.
If I understand correctly, electrical semiconductors are also thermal superconductors, though the converse isn't true (thermal superconductors don't have to be electrical superconductors).
I could be mistaken about this, but I've seen references in a couple of places.
Re. thermal superconductors, I remember seeing a reference to "superconductor-like behaviour" being observed at room temperature. I was told that this was thermal superconduction, though I have no way to substantiate this rumour.
Can anyone familiar with the original article pass on what "superconductor-like behavior" means?