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Bell Labs claims to have found new limit for chip size
Nocturna writes "SiliconValley.com reports scientists at Bell Labs claim to have found a new limit on how small they can make chips, doubling the life left in silicon technology. " Essentially, what Bell Labs is saying that you can't go any smaller then 5 atoms of silicon dioxide at the heart of the machine. As before, they are saying that this the limit-although this time it may veryw ell be true, with current materials.
When current flows through a wire, atoms in the wire tend to be dragged along with the current. The current density - current per unit cross-sectional area of the wire - has to be kept below safe limits (dependent on temperature) to prevent this. Faster chips are made by passing the same amount of current through smaller transistors - but this means through smaller wires, too. Electromigration limits how small you can shrink the wires before your chip dies an early death. Copper helps - it is much more resistant to electromigration than aluminum - but it's still a big problem, and will keep getting bigger.
You get capacitive coupling between wires that are close together - signal leaks from one to the other. This is worse for wires that are closer together, and worse for higher frequencies. As chips shrink and are clocked more quickly, capacitive coupling becomes an ever-greater problem. Capacitive coupling also causes signal leakage between the various parts of a transistor, as well as between transistor sources/drains and the substrate (though silicon-on-insulator helps eliminate this last effect).
A chip's total parasitic capacitance doesn't depend that much on the size of its transistors; just on its total area. Charging and discharging this capacitance dissipates a certain amount of energy (dependent on the chip voltage). As chips are clocked more quickly, power dissipation goes up in proportion to the clock speed. Reducing the core voltage helps a bit, but the core voltage must always be considerably higher than the transistor threshold voltage. Silicon-on-insulator lowers the total parasitic capacitance, but only to a certain point. The problem remains.
This list completely ignores fabrication difficulties at finer linewidths, though those look like they're tractable. However, electrical problems will still pose limits to how small you can shrink features on a chip. When exactly these limits will come into play remains to be seen, but they are lurking.
There are two obstacles that I can think of. The first is heat disspiation; heat will have to travel farther through the chip before reaching the surface. This could be ameliorated by putting sheets of thermally conducting material between layers, but this is complicated, and they'd have to be pretty thick (unless they were thermal superconductors; IIRC these exist at room temperature).
The other obstacle is depositing a layer of crystalline silicon to make transistors with. Current wafers are still sliced from single crystals of silicon. However, silicon that is deposited tends to be polycrystalline. This gives it poor electrical properties.
We'd either have to figure out how to grow or place single-crystal layers of silicon on to an outer oxide layer of a chip, or else figure out how to make fast circuitry with polycrystalline silicon.
That having been said, this is an idea that I like very much. It is one of the logical ways of extending chips once linewidth reaches its limits.
That must mean my house is very low power - it only has 60 Hz of power! How will I be able to power one of these chips if my house doesn't have enough power?