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SMP Linux on the Cheap
d^2b writes "There is an article using dual Celerons under Linux on cpureview.com.
This is even more attractive now that you
can buy an Abit BP6 for $130 and
plug two socket 370 Celerons into it directly.
The good news is that that author gets 183%
speedup over a single processor compiling the kernel. "
I did it! My lone Celeron 300A is now 504MHz. Doesn't seem any faster, but RC5 might be able to crunch a few more keys... I had to change the core voltage to 2.4volts and set the BIOS to ignore the "error" of this higher voltage. The CPU did not like 2.0volts and scrambled the eggs on the hard drive with 2.2volts while compiling the kernel. The CPU does not seem to put out any heat, so 504/113MHz it is!
The idea of using Celerons only works if you can overclock them. It may go well for hacks and tinkers, but for the heavy video and I/O, a 66Mhz bus frequency is unacceptable.
In the article, the guy ran one of the chips at 2.1 volts... I wonder how long it stayed stable at that speed/voltage. I have a C300A that runs perfectly stable at 450 MHz 1.9v, but crashes regularly if I use default 2.0 voltage. These PPGA Celerons don't dissipate heat as well as their Slot-1 brothers can.
I would expect memory bandwidth to be an issue with SMP Celeron systems, especially if you're not overclocking. The last part of the article touched on this, but I think a lot of people still don't get it...
The Celerons only have 128k cache, compared to 512k on the P2. The Celeron cache runs at twice the speed of the P2 cache, often resulting in better single-processor performance, but because the Celeron cache is smaller it has to go to RAM more often. This means that the Celerons consume more memory bandwith than the P2s.
Combine this with the fact that an un-OCed Celeron runs with only a 66 MHz bus, compared with 100 MHz for a P2. Even though the Celeron needs more memory bandwidth than a P2, it gets less.
Now stick two of these bandwidth-hungry chips on the same board accessing the same 66 MHz RAM...
I suspect it would not be worth it unless you used 300As at 450+ (100+ MHz FSB).
Does anyone have performance numbers for un-overclocked Celeron SMP?
Its not a SMP with my P2B motherboard, but I have tried my Celeron at 503MHz with the bus speed at 113MHz and it will run for about ten minutes before the kernel oops with a memory page error. Its been running at 463/103MHz since October without a glitch. Has anyone had success with a 113MHz bus speed?
But there are places that will sell you a tested overclocked celeron system.
I cam across this one the other day:
http://www.becomputing.com
Ben
The celerons are underclocked to begin with. The core is the same as that of the PIIs running at 100 FSB.. The only issue should be the cache. I run dual 300As at 450 with no issues. The CPUs don't even really heat up that much.
From what i've seen, the biggest issue when doing SMP OC'ed celerons is the MB and the slockets.
Intel CPUs are tanks.. I've worked at a computer store for over two years.. Since the day I've started we've had a total of 3 intel CPUs ever fail (including DOA).. I've seen some techs/customers do some pretty evil things and the CPU just gets up and runs again.. In one case a computer was caught in a lightning storm, and the line surged. Took everything out but the CPU.
Besides, even if you did manage to break a celeron, they're cheap as hell. My MB cost more than both CPUs and the adapters.
I think everyone should at least look into Dual Celerons for their next upgrade. Highest bang-for-your-buck ratio i've ever seen.
Check out Hot Hardware and HardOCP for the scoop.
--
The idea of using Celerons only works if you can overclock them. It may go well for hacks and tinkers, but for the heavy video and I/O, a 66Mhz bus frequency is unacceptable. The chances of overclocking single celerons to a 100Mhz bus is 75%. For both processors in a dual processor system, the success drops to 56%. Also since people are much less willing to report failure publicly, the percentages may even be lower in real life. You won't see anyone post a failed overclock on slashdot.
I built this system with an MTech M668DS LX chipset dual slot 1 motherboard, matrox G200, 128 megs of 6ns ECC SDRAM.
I'm using two celeron 366's on pre-modified MSI MS-6905's. I am not overclocking.
Doesn't work worth a damn. My uptimes range from 3 hours to 2 days. It's like using Windows or something.
If it were a memory problem, I'd see ECC complaints all over my logs. My cpu's have huge heatsinks and lmsensors report that they rarely get over 44c, so it can't be heat.
It usually crashes when the system is doing nothing more complex than animating the "Ifs" xscreensaver module. It never has crashed during a kernel compile, though i recompile every week or so, and use make -j4.
At this point, all I can figure is that the slotkets are defective. I don't expect to get a refund from the place i bought them from. I've ordered (far more expensive) PowerLeap slotkets on the off chance they might work better.
If that doesn't work out, I'm probably tracking down a pair of PII-333's. Which would suck, because this system performs very well when it's not locked up.
This is just like television, only you can see much further.
Here's a story at Ars Technica comparing dual Celerons to dual PIII's, both oc'ed. Results were suprising, to say the least.
(I don't believe this is a fluke, either. My machine is basically the nerd box, but at 464, and it is thus far is proving to faster than I expected, close to PIII 500 speed (without SSE, of course).)
I've heard that when you overclock the 466's the bus speed is so out of whack that alot of peripherals don't function anymore. The guys at computernerd.com say the best setup is a pair of 366s overclocked to 550.
Just curious, now that Celerons have the locked multiplier, could I run a 4.5x and a 5.0x (300a and a 333a) in SMP? I currently have a dual 300a/504 system, but it has occurred to me that:
a) On old systems, the multipliers were set at one spot on the motherboard
b) The processors don't know what the multiplier settings of other processors are
c) They communicate to each other at the bus speed
This to me would mean it is entirely possible.
I know people who have gotten a PII and a Celeron to work. Anyone want to take a stab if you can have to different multipliers?
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