8 way SMP chipset for K7
Bill Henning writes "For those of you interested, HotRail has announced an 8 way SMP chipset for the K7 using crossbar switching to improve SMP performance; Read more in this article
" So much speed, so many RC5 keys to crack.
I have never bought anything but an AMD. I have been pleased w/ their products. However, AMD, Intel, IBM, etc. have made their processors so complex that trying to add in a major feature like SMP causes all sorts of problems & can make the setup slower than a single cpu by itself if the SMP technique is not well thought out. Problems like keeping caches in sync and so forth are being encountered but for the wrong reasons. Cache logic was instituted because memory was slower than the cpu & since most of what you do is access memory, it was the most cost effective way to speed up memory access. However, now they want to setup smp between the systems. Cache logic automates the cache so that the programmer is "unaware" of its presence. That may be great for a single processor, but when you hit SMP, it provides the potential for multiprocessor performance to go into the toilet. If you want to see a cool processor design, go to www.ultratechnology.com & read about Chuck Moore & his forth chips. 27 instructions & they run as 500mhz. Guess what, no cache... His design does not require any. Only one downside to his chips, he only makes 20bit processors (please Chuck, make a 32 bit/64 bit). His transistor count is way down too. Around 20000! So you take an intel wafer & put a 32/64 bit version of Chucks chip on it plus about 256mb of 500mhz ram! Maybe some day chip vendors will learn. I don't have a problem w/ making something complex. As long as it is "necessary" complexity. If Chuck does make a 32/64 bit version, I will have my Masters in electrical engineering in a few years & guess who will be building his own PC... Well, that is my 2 cents.