8 way SMP chipset for K7

Bill Henning writes "For those of you interested, HotRail has announced an 8 way SMP chipset for the K7 using crossbar switching to improve SMP performance; Read more in this article " So much speed, so many RC5 keys to crack.

Comments

Modern chips are overly complex...

[Dark Fire]

I have never bought anything but an AMD. I have been pleased w/ their products. However, AMD, Intel, IBM, etc. have made their processors so complex that trying to add in a major feature like SMP causes all sorts of problems & can make the setup slower than a single cpu by itself if the SMP technique is not well thought out. Problems like keeping caches in sync and so forth are being encountered but for the wrong reasons. Cache logic was instituted because memory was slower than the cpu & since most of what you do is access memory, it was the most cost effective way to speed up memory access. However, now they want to setup smp between the systems. Cache logic automates the cache so that the programmer is "unaware" of its presence. That may be great for a single processor, but when you hit SMP, it provides the potential for multiprocessor performance to go into the toilet. If you want to see a cool processor design, go to www.ultratechnology.com & read about Chuck Moore & his forth chips. 27 instructions & they run as 500mhz. Guess what, no cache... His design does not require any. Only one downside to his chips, he only makes 20bit processors (please Chuck, make a 32 bit/64 bit). His transistor count is way down too. Around 20000! So you take an intel wafer & put a 32/64 bit version of Chucks chip on it plus about 256mb of 500mhz ram! Maybe some day chip vendors will learn. I don't have a problem w/ making something complex. As long as it is "necessary" complexity. If Chuck does make a 32/64 bit version, I will have my Masters in electrical engineering in a few years & guess who will be building his own PC... Well, that is my 2 cents.

When?

[abischof]

Anyone know when these SMP boards are going to be available?

Also, since CmdrTaco mentioned it, are there any estimates for the K7's rc5 speed?

Alex Bischoff
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Finally a non-Intel SMP solution for x86...

[Khyron]

The article isn't that bad, at least, it's more informative than most of the crap you usually have to read looking for real information in an industry typically reported on by twits who know nothing of it.

Personally, despite some of the valid criticism people will make of this technology I am just pleased about what it means to the processor scene - at last x86 systems will be able to be built with multiple CPU's using non-Intel CPU's!

Now personally, yes, I have always been a big fan of AMD, I have several machines at home running on K6 series chips right now, but AMD zeal is not why this makes me happy. This makes me happy simply because I want to see more competition in the higher end x86 system market where chips are concerned. For years typical home and office single user PC builders have had choices and competition which has driven down prices. Hopefully, this kind of technology and the possibilities it opens will create more competition and freedom of choice in the higher end markets for the serverheads and rendermonkeys who need the heavy multiple CPU horsepower but until now have had little choice where x86 architechture was concerned.

SAVE THE BATS

How crossbars work, really.

[Airdevronsix Icefall]

The person who wrote this article clearly hasn't thought about crossbars
very much. It's all about how hard it is to put a big crossbar on a
single chip. But the author has apparently never dealt with an actual
crossbar. I used to design supercomputers back in the '80s, and we had it
even worse than they do nowadays, as far as how many pins you could get on
a chip. And yet, we managed to design and even build big crossbars. How
did we do it?

We split the data path across multiple chips. The way this
applies to the example at hand is to build a chip that can switch among 14
ports, each only 16 bits wide. This will require a failrly reasonable 224
pins on the chip. Then you gang these chips up, with one switching data
bits 0 to 15, one switching 16 through 32, etc. To switch a
128-bit-wide bus, you need 8 of these chips. You also need to design a
control chip to look at the address and control lines to decide which
processor to connect to which memory on each clock cycle. The control
chip broadcasts identical switching instructions to all the data chips.

This solution keeps you from having to multiplex pins, and it keeps you
from having to build stupendous 1000-pin packages, and it keeps you from
having to run busses at 800 MHz and turn your computer into a microwave
oven. The only downside is that you need a set of nine chips, but on a
motherboard that aleady has eight processors, that's not too bad.

--Carl Feynman