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Field Programmable Gate Arrays at MIT
Rhys Dyfrgi writes "There is an article in this month's Scientific American about the Raw microchip. Based around field programmable gates arrays, they claim it will reach speeds between 10 and 15 gigahertz by the year 2010. Because it's a FPGA, it can be instantly reconfigured to perform any task. It is one of the central items for the Oxygen Project. "
I like the scenario they describe: "You are on business in Paris. You excuse yourself from the meeting, go outdoors, pull out your handy and ask it to contact Joe."
Joe admits to being flattered, maybe a little curious, but is happily married and suggests you put your handy away before somebody sees the two of you and starts spreading rumors.
Unfortunately, there's a bit too little of #5 lately, and too much of all the other crap.
10 PRINT CHR$(205.5+RND(1)); : GOTO 10
MEEPT!! is an eccentric user of slashdot who has been posting for nearly two years or so. He used to post a lot more in earlier times, but ever since Slashdot killed his account, forcing him to create a new one, he seems to be a less frequent visitor. His posts are usually insightful, but he presents his arguments/information in a humorous or unusual way, such as haikus and other poems, leading many people to misunderstand him. He's also not a Linux zealot, which gets him in trouble with many of the fanatics around here. I personally find him humorous.
"The glorious MEEPT would like to bring all the divided factions of linux into one big divided faction." - The Glorious MEEPT!!
10 PRINT CHR$(205.5+RND(1)); : GOTO 10
Since I have done been researching Slashdot for over 20 years now with a broad range of test subjects from around the world, I have discovered that these comments are posted, without fail, no matter what the article, and usually before the poster has read the article. I will cover them here so no one needs to say them and waste more vaulable space:
1) Does it run Linux?
2) How about a Beowulf cluster(an alteration goes like "Damn, wouldn't a Beowulf cluster of (insert computer chip, iBook, Red Hat Stock, anything really, in here) be sweet?")
3) This isn't news for nerds!
4) FIRST POST
5) MEEPT
6) MS Sucks
7) Apple sucks
8) Where can I get the source code?
9) No source code? Damn this thing is a piece of shit.(note, source code is required even if the item in discussion does not have source code, it's a freedom thing)
If I have missed any, please feel free to contribute to the standard Slashdot response. Once we have a good list, we should work on making a program that will automatically go to a story and post one of these comments at random, saving valuable time for the people who would have had to spend that time letting their brain rot while they typed.
Right now I hold Starbridge Systems in as much esteem as I hold American Computer. Starbridge systems makes provably bogus performance claims. They're not overstated nor are they misleading, they're bogus. Maybe they do have something but their marketing department is overzealous and/or stupid, either way having such obviously false information sure makes it look like a scam.
People who have programmed FPGA realize that the claim FPGAs run at a faster clock rate are
missing the point.
Creating a chip architecture/micro-architecture is a function of 4 fundamental tradeoffs:
Cycle time, Work per cycle, Area, and Time to market.
FPGA have chosen low work per cycle. In the past, CPUs chose high work per cycle.
Now, they are going in the direction of lower work per cycle (deeper pipelines, more latency).
Just a question of what you want.
Clock rate is just one choice of many, and has little to do with some magic FPGA architecture.
In fact with today's fpga, 200MHz is fast, compare that to your 450MHz pentium III...
The main architectural advantage of FPGAs is that a block of logic only needs to exist when you
are using it. This is simply a form of caching. Instead of having all the HW there (but slower),
you have only the subset you need (so it's faster). However, if you factor in the "misses"
(the time where logic has to be reprogrammed), it's a much more complicated problem which
doesn't have such an "obvious" solution...
Just like there are data sets that blow a CPU cache, there are probably algorithms that make
re-programmability a liability.
On the issue of efficiency, FPGA just have underused programmability and routing logic
instead of underused HW functional units in other architectures. Depends on the problem you are
trying to solve...
-slew
what did you think of the book?
I believe Starbridge Systems has already sold a supercomputer with a FPGA processor and is developing what they call "a new personal supercomputer that will change the PC industry forever". This has already been posted on /. before. Still very interesting though. They also say "SBS's Hypercomputer systems can emulate virtually any hardware, including other supercomputers", so running Linux or *BSD on it shouldn't be much of a problem :)
0x or or snor perron?!
[Apologies if this sounds familiar to long-time readers; I've said this before and I believe it bears saying again.]
In addition to the lower native gate speed and inefficiencies of cell-based logic of FPGAs vis a vis full-custom processors, there's a serious problem with the time it takes to reprogram an FPGA. To put this in perspective, let's say that the time to perform computational work can be expressed as AX+B, where A is the time to perform an operation, X is the number of times the operation is repeated before moving on to a different operation, and B is the time to program that operation into the processor. For a traditional processor, B is zero. For an FPGA, A might be smaller than it is for the traditional processor, but B is very large. It doesn't take a rocket scientist[1] to figure out, therefore, that FPGAs win when X is large, i.e. when a task is very highly repetitive. There are a lot of tasks that fit this mold - audio and video processing, discrete-element simulations, etc. - but many of the most common everyday computational tasks you and I might face do not. For those cases, reprogramming overhead would be a killer.
Is there hope? Yes, absolutely. Lots of people are working on faster reprogramming, because it's known to be the One Big Problem in reconfigurable computing. Even better, work on partial reprogrammability is increasing. This is really cool because it would essentially allow you to dedicate part of the processor to functions you always need[2], and then use the rest to cache logic very much as data is cached now. In its simplest form, this could mean that all the parts of a traditional processor except for the actual functional units are permanent, and the cached items are instructions much like the instructions we have today. Need a population-count instruction? Allocate logic space and an opcode, reprogram the space, and voila! When you no longer need that instruction it'll fall out of the cache to be replaced by another instruction you do need. Of course, when the von Neumann model itself becomes the bottleneck then maybe the cached items would have interfaces other than instruction opcodes and register files, but defining those interfaces to allow the sort of logic-caching I've described is still a major conceptual problem worthy of a doctoral thesis or two.
[1] What's so special about rocket scientists, anyway? There are plenty of professions nowadays requiring greater knowledge and skill.
[2] The permanent part could even be implemented full-custom style, while the reprogrammable part remains cell-based. Altera had something called an SPGA which was like this, but I can't find it any more.
Slashdot - News for Herds. Stuff that Splatters.
Actually, the use of ISA to mean "Instruction Set Architecture" may well predate it use to mean "Industry Standard Architecture". In any case, both meanings have been around for a long time and we might as well get used to them. It wouldn't be the only time the same acronym had two very distinct meanings. ATM, anyone?
Slashdot - News for Herds. Stuff that Splatters.
>FPGA's can run at much higher clock frequencies then current CPU's because of fundamental architectural differences.
That is incorrect. Gate speeds for FPGAs are _lower_ than for full-custom silicon.
Slashdot - News for Herds. Stuff that Splatters.
Yes, it reminds me of another programmable gate array article posted on slashdot a couple of months ago. That one was a bit difficult to believe also. Personally, I wonder about the complexity of the "compiler" that will run these things.
One thing you can say for them: like the company in the earlier article, they have no shortage of self-confidence!
Geeky modern art T-shirts
There's a really interesting article on New Scientist, Creatures from Primordial Silicon, on the application of genetic algorithms to FPGA chips. In this case, the researcher was able to let natural selection design a chip that was capable of producing a 5v output when he said "Start" and stop producing the output when he said "Stop".
The cooler part is that no one can figure out how the chip works; he didn't implement a clock -- one evolved using fewer components than the simplest example given in any engineering text. There are a few components in there that don't seem logically neccessary, but their removal results in a non-functional chip. Theoretically, using the evolutionary procedure allowed the chip to utilize subtle properties of the materials used in its composition, like the small resistance changes caused by heat or electromagnetic induction.
It's a good read if you're interested.
"h3y 1c3 kr34m!! 4r3 j00 3r33+!?" "y3z crackd, 4nD n0w 3y3 w1lL h4xx0r j00r m0u+h! h0h0h!!0"