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Field Programmable Gate Arrays at MIT
Rhys Dyfrgi writes "There is an article in this month's Scientific American about the Raw microchip. Based around field programmable gates arrays, they claim it will reach speeds between 10 and 15 gigahertz by the year 2010. Because it's a FPGA, it can be instantly reconfigured to perform any task. It is one of the central items for the Oxygen Project. "
People who have programmed FPGA realize that the claim FPGAs run at a faster clock rate are
missing the point.
Creating a chip architecture/micro-architecture is a function of 4 fundamental tradeoffs:
Cycle time, Work per cycle, Area, and Time to market.
FPGA have chosen low work per cycle. In the past, CPUs chose high work per cycle.
Now, they are going in the direction of lower work per cycle (deeper pipelines, more latency).
Just a question of what you want.
Clock rate is just one choice of many, and has little to do with some magic FPGA architecture.
In fact with today's fpga, 200MHz is fast, compare that to your 450MHz pentium III...
The main architectural advantage of FPGAs is that a block of logic only needs to exist when you
are using it. This is simply a form of caching. Instead of having all the HW there (but slower),
you have only the subset you need (so it's faster). However, if you factor in the "misses"
(the time where logic has to be reprogrammed), it's a much more complicated problem which
doesn't have such an "obvious" solution...
Just like there are data sets that blow a CPU cache, there are probably algorithms that make
re-programmability a liability.
On the issue of efficiency, FPGA just have underused programmability and routing logic
instead of underused HW functional units in other architectures. Depends on the problem you are
trying to solve...
-slew