companies that make voting machines don't deserve to be in business.
i'd like to see someone prove that there is ROI in purchasing a souped up 74LS163 for huge amounts of money when I'm pretty sure you can get protein machines to volunteer to count paper ballots redundantly in a way that is transparent, fair and verifiable by mere mortals.
voting machines are expressions of Skynet trying to put a computer where it doesn't need to be, just to take humans out of the loop.
It's tends to be harder to get an FPGA to "hello world" but it seems these days that all the cool kids are compiling their dataflow graphs into reconfigurable logic. If you want to be a 1337 fpga programmer, then you should learn Bluespec. Guarded atomic actions for the masses!
The BEE boards are being trumpeted as multicore experimentation environment, but the FPGA itself is a powerful computational engine in its own right. FPGAs have to overcome the inertia of their history as verification tools for ASIC designs if they want to grow into being algorithm executers in their own right.
There's a growing community of FPGA programmers making accelerators for supercomputing applications. DRC (www.drccomputing.com) and XtremeData (www.xtremedatainc.com) both make co-processors for Opteron sockets with HyperTransport connections, and Cray uses these FPGA accelerators in their latest machines. There is even an active open standards body (www.openfpga.org).
FPGAs and multicore BOTH suffer from the lack of a good programming model. Any good programming model for multicore chips will also be a good programming model for FPGA devices. The underlying similarity here is the need to place dataflow graphs into a lattice of cells (be they fine-grained cells like FPGA CLBs or coarse-grained cells like a multicore processor). I can make a convincing argument that spreadsheets will be both the programming model and killer-app for future parallel computers: think scales with cells.
I've kept a blog on this stuff if you still care: fpgacomputing.blogspot.com
Steve Jobs is successful where the RIAA wasn't because he learned how to compete with free with better instead of with whining.
Another argument against neutrality is that you can't pay to have ISPs allocate more bandwidth for your torrent service.
the impetus for adding restrictions and obfuscations is most certainly NOT security in the DoD sense. methinks interested parties are trying to juxtapose priacy/DRM interests with security/terrorism concerns. there is no really good argument for increased in-silicon DRM as a means to end-to-end security except for the economic security of intellectuals and their property.
the troubling aspect to any attempt at subverting counterfeit designs is that it encourages mechanism to obfuscate a digital design and decreases your freedom to know exactly what is happening to those electrons. such measures invariably decrease the overall security and reliability of the system by adding more complexity. an easily counterfeit-able design is also easy to verify. the converse is also true.
truly safe systems must incorporate redundant standardized parts from multiple vendors to eliminate the effectiveness of malevolently embedded flaws.
the hard part is, of course, how do we program it; there are plenty of applications that benefit from parallelization (graphics processing, SDR, FEM). parallelization tends to offer equivalent throughput at a lower rate of switching. we need to review whether high frequency switching is really worth the power when you have trillions of transistors in a cubic centimeter. at todays price for 1 million gate FPGA, a 1 trillion gate FPGA array would cost about $10-20M, I expect this will be down by a factor of 1000 in under 10 years. operating at 100 MHz it would be hard to not have a petaflop of computation.
lower frequency requirements lets us get creative with power. power density (temperature) is directly related to the number of switching capacitance in a region. lower frequency circuits and asynchronous circuits can reduce the effect of the most major sources of switching (clock). with adiabatic logic systems you can actually use charge pumping and charge recovery to eliminate capacitive loss during switching but these circuits operate slower. when you combine asynchronous and adiabatic logic you can actually use the REQ-ACK handshake as a charge pump to power on functional units.
and if you really want high frequency switching, you'll need to remove thermal energy. one of the early uses of carbon nanotubes in circuits may be as thermal channels. it's also possible to create submersible circuitry using microfluidic ducts to cool wafer-stacked chips.
Moore's law is an observation about the cost per transistor in a circuit. Making faster computation is all about transistor density and the distance signals must travel. Even after the 2-D transistor density levels off, the race will be on to make cheaper 3-D chips using wafer-bonding methods, giving us a new dimension to increase density and thus speed up computation: http://mtlweb.mit.edu/researchgroups/icsystems/3dcsg/
And we'll still see the same exponential benefits to GOPs/$ for a long time after 3-D transistor density maxes out. The economics that drive the exponential cost-per-computation trend are more related to volume of demand which offsets high fixed production costs and less related to our ability to actually cram more transistors on a chip.
There is a terminology problem in referring to FPGA configurations as "Hardware." An FPGA core is a different sort of entity from Hardware or Software; the term Configware is increasingly popular term for it.
The description of the algorithm should be abstracted from the metal executing a particular manifestation of the algorithm and so the licensing issues for configware are no different than licensing issues for software. Similar to issues in the traditional software world, a stumbling block for FPGA adoption is integrating proprietary cores with open source components.
An interesting and difficult problem is making compilers from various linguistic paradigms to execution models appropriate for FPGA hardware or instruction stream processors. Bluespec is an example of a language that can compile to C and Verilog.
>>And if I have to ignore one more invitation to a Ron Paul supporters group on facebook I'll scream.
that's just their way of superpoking you.
It was a Ron P'All Your Base Are Belong To Us' after all:
http://ronpaulchocolate.com/ronpaulaybabtu.jpg
Austrian economists say that people act irrationally thus questioning traditional macroeconomic models of supply and demand equilibrium. It is more of a philosophical basis for Libertarian economic policy rather than an analytic model for macroeconomic trends. An individual's notion of value is psychological and time-varying. To transform psychological proclivities into statistical variables is a proven way to profit, but it calls into question the very meaning of a value.
Do you really think paper money has value except through mass hypnosis?
How about illegal prime numbers?
Who the hell ever thought it was a good idea to let a robot count our votes? Can't we just use mechanical turks that cost less to maintain? There are probably enough protein machines willing to do it in an open and secure manner and for free. It just seems like a ludicrous waste of money, certainly not worth the ROI for something used a couple days out of the year. The risk of tampering is also obvious since Diebold must have friends in political places to convince them to grossly overpay for a few 74LS163s
Are proponents of electronic voting trying to make their protein counterparts obsolete?
"One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage."
leakage is more dependent on threshold voltage than Vds. running a chip subthreshold means you are relying on leakage to charge up capacitance. we've had this research going on for years at MIT.
subthreshold circuits with dynamic voltage scaling are fun and stuff, but the real issue at small geometries is leakage currents which constitute the majority of power consumption. Traditional dynamic voltage scaling doesn't help much because leakage is dominated by the threshold voltage not the power rail. multi-threshold CMOS uses enable signals to turn on and off high leakage paths. this does not help with active mode leakage when the system does not need to operate at full speed. to reduce active mode leakage we need to do dynamic threshold scaling requires body-bias modulation which is currently an expensive process in terms of IC production.
other sexy low power technologies: adiabatic logic (charge recovery), and asynchronous logic (the majority of power is consumed by the clock so let's get rid of it).
most of/. supports Ron Paul. the IT industry's productivity and Ron Paul search traffic are inversely correlated.
and it is natural that engineers should support paul: he's obviously the socrates of this election. engineers are used to hearing someone assert "XXX is not possible" and declaring that indeed "XXX is possible." Ergo Ron Paul. the "subvert the dominant paradigm" candidate '08
Ron Paul's candidacy is a lesson in self-fulfillment: he cannot win because there are not enough engineers willing to convince you that he can win. And since he can't win, he must be bat-shit crazy for trying. And then there's the wacky supporters that drink a little too much bongwater-kool-ade. Libertarianism was cooler when it wasn't being made fun of cuz of the hippies.
Mostly, I think haters are just jealous that Dr. Paul is a bit of a nerd but has seen more vagina than even some dedicated porn collectors.
A lot of you seem to be missing the point and dismissing the article as system to allow designers to be lazy and release "faulty designs." The article was less about allowing bad designs and more about allow defective chips to work thereby increasing yield and product life.
Defect tolerant arrays are still not a new idea. Every single Playstation 3 that ships is assumed to have a defective SPU in it so that the Cell yield could be higher and thus the PS3 could be cheaper. FPGAs are an array of finer grained processing elements and thus have lower susceptibility to defects. Many people note that FPGAs suffer a performance hit to ASICs, though an FPGA is more comparable to a CPU than an ASIC since it is a general purpose device. There are many processing tasks on which an FPGA can achieve order of magnitude higher performance than a CPU due to parallelization and I/O efficiency. Some people said that the cost of FPGAs is very high. This is simply no longer the case: the Xilinx Spartan 3E chips can implement 1M gate designs for about under 10$. Higher performance FPGAs have cost factors which are largely attributable to market demand and any economic comparison with CPUs should be normalized to account for volume. Even still, if cost/gate scales linearly one could currently devise a 1 Trillion gate FPGA for $10M based on the Spartan's costs. Even if I'm a factor of 10 off on cost, it would be the most powerful supercomputer in the world at a bargain price.
Chip defect density will increase with decreasing transistor size to a point where the most economically viable chip is a defect tolerant array that can eliminate much of the semiconductor testing and yield costs.
The major missing piece is an operating system for these things to provide a simple and transferable programming model.
Slashdot Mirror
companies that make voting machines don't deserve to be in business.
i'd like to see someone prove that there is ROI in purchasing a souped up 74LS163 for huge amounts of money when I'm pretty sure you can get protein machines to volunteer to count paper ballots redundantly in a way that is transparent, fair and verifiable by mere mortals.
voting machines are expressions of Skynet trying to put a computer where it doesn't need to be, just to take humans out of the loop.
Alternatively, in VHDL:
/= CPU
FPGA
It's tends to be harder to get an FPGA to "hello world" but it seems these days that all the cool kids are compiling their dataflow graphs into reconfigurable logic. If you want to be a 1337 fpga programmer, then you should learn Bluespec. Guarded atomic actions for the masses!
Or Excel
The BEE boards are being trumpeted as multicore experimentation environment, but the FPGA itself is a powerful computational engine in its own right. FPGAs have to overcome the inertia of their history as verification tools for ASIC designs if they want to grow into being algorithm executers in their own right.
There's a growing community of FPGA programmers making accelerators for supercomputing applications. DRC (www.drccomputing.com) and XtremeData (www.xtremedatainc.com) both make co-processors for Opteron sockets with HyperTransport connections, and Cray uses these FPGA accelerators in their latest machines. There is even an active open standards body (www.openfpga.org).
FPGAs and multicore BOTH suffer from the lack of a good programming model. Any good programming model for multicore chips will also be a good programming model for FPGA devices. The underlying similarity here is the need to place dataflow graphs into a lattice of cells (be they fine-grained cells like FPGA CLBs or coarse-grained cells like a multicore processor). I can make a convincing argument that spreadsheets will be both the programming model and killer-app for future parallel computers: think scales with cells.
I've kept a blog on this stuff if you still care: fpgacomputing.blogspot.com
Steve Jobs is successful where the RIAA wasn't because he learned how to compete with free with better instead of with whining. Another argument against neutrality is that you can't pay to have ISPs allocate more bandwidth for your torrent service.
the impetus for adding restrictions and obfuscations is most certainly NOT security in the DoD sense. methinks interested parties are trying to juxtapose priacy/DRM interests with security/terrorism concerns. there is no really good argument for increased in-silicon DRM as a means to end-to-end security except for the economic security of intellectuals and their property. the troubling aspect to any attempt at subverting counterfeit designs is that it encourages mechanism to obfuscate a digital design and decreases your freedom to know exactly what is happening to those electrons. such measures invariably decrease the overall security and reliability of the system by adding more complexity. an easily counterfeit-able design is also easy to verify. the converse is also true. truly safe systems must incorporate redundant standardized parts from multiple vendors to eliminate the effectiveness of malevolently embedded flaws.
apparently the latest fad is to inject your kid with an RFID at birth.
i voted ron paul. get a sense of humor ;) i worked on computers at ORNL. i get it.
If we elect a republican president all of our supercomputing capacity will be put toward: "Who would Jesus Bomb?"
the hard part is, of course, how do we program it; there are plenty of applications that benefit from parallelization (graphics processing, SDR, FEM). parallelization tends to offer equivalent throughput at a lower rate of switching. we need to review whether high frequency switching is really worth the power when you have trillions of transistors in a cubic centimeter. at todays price for 1 million gate FPGA, a 1 trillion gate FPGA array would cost about $10-20M, I expect this will be down by a factor of 1000 in under 10 years. operating at 100 MHz it would be hard to not have a petaflop of computation. lower frequency requirements lets us get creative with power. power density (temperature) is directly related to the number of switching capacitance in a region. lower frequency circuits and asynchronous circuits can reduce the effect of the most major sources of switching (clock). with adiabatic logic systems you can actually use charge pumping and charge recovery to eliminate capacitive loss during switching but these circuits operate slower. when you combine asynchronous and adiabatic logic you can actually use the REQ-ACK handshake as a charge pump to power on functional units. and if you really want high frequency switching, you'll need to remove thermal energy. one of the early uses of carbon nanotubes in circuits may be as thermal channels. it's also possible to create submersible circuitry using microfluidic ducts to cool wafer-stacked chips.
Moore's law is an observation about the cost per transistor in a circuit. Making faster computation is all about transistor density and the distance signals must travel. Even after the 2-D transistor density levels off, the race will be on to make cheaper 3-D chips using wafer-bonding methods, giving us a new dimension to increase density and thus speed up computation:
http://mtlweb.mit.edu/researchgroups/icsystems/3dcsg/
And we'll still see the same exponential benefits to GOPs/$ for a long time after 3-D transistor density maxes out. The economics that drive the exponential cost-per-computation trend are more related to volume of demand which offsets high fixed production costs and less related to our ability to actually cram more transistors on a chip.
I guarantee that there is no logic to insurrection when these sorts of weapon can be made quite cheaply: http://www.youtube.com/watch?v=Nc3vcXp_7O8 - SuperSoaker Flamethrower http://s80.photobucket.com/albums/j187/hsvzclubbie/?action=view¤t=Attack_Chopperwmv.flv - RC Helicopter with Machine Gun Basically we have to watchout for Botnets of RC Helicopters with Guns and Supersoaker Flamethrowers controlled by some wireless ethernet protocol we can affectionately refer to as skynet.
There is a terminology problem in referring to FPGA configurations as "Hardware." An FPGA core is a different sort of entity from Hardware or Software; the term Configware is increasingly popular term for it. The description of the algorithm should be abstracted from the metal executing a particular manifestation of the algorithm and so the licensing issues for configware are no different than licensing issues for software. Similar to issues in the traditional software world, a stumbling block for FPGA adoption is integrating proprietary cores with open source components. An interesting and difficult problem is making compilers from various linguistic paradigms to execution models appropriate for FPGA hardware or instruction stream processors. Bluespec is an example of a language that can compile to C and Verilog.
>>And if I have to ignore one more invitation to a Ron Paul supporters group on facebook I'll scream. that's just their way of superpoking you. It was a Ron P'All Your Base Are Belong To Us' after all: http://ronpaulchocolate.com/ronpaulaybabtu.jpg
Austrian economists say that people act irrationally thus questioning traditional macroeconomic models of supply and demand equilibrium. It is more of a philosophical basis for Libertarian economic policy rather than an analytic model for macroeconomic trends. An individual's notion of value is psychological and time-varying. To transform psychological proclivities into statistical variables is a proven way to profit, but it calls into question the very meaning of a value. Do you really think paper money has value except through mass hypnosis? How about illegal prime numbers?
Who the hell ever thought it was a good idea to let a robot count our votes? Can't we just use mechanical turks that cost less to maintain? There are probably enough protein machines willing to do it in an open and secure manner and for free. It just seems like a ludicrous waste of money, certainly not worth the ROI for something used a couple days out of the year. The risk of tampering is also obvious since Diebold must have friends in political places to convince them to grossly overpay for a few 74LS163s Are proponents of electronic voting trying to make their protein counterparts obsolete?
"One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage." leakage is more dependent on threshold voltage than Vds. running a chip subthreshold means you are relying on leakage to charge up capacitance. we've had this research going on for years at MIT.
subthreshold circuits with dynamic voltage scaling are fun and stuff, but the real issue at small geometries is leakage currents which constitute the majority of power consumption. Traditional dynamic voltage scaling doesn't help much because leakage is dominated by the threshold voltage not the power rail. multi-threshold CMOS uses enable signals to turn on and off high leakage paths. this does not help with active mode leakage when the system does not need to operate at full speed. to reduce active mode leakage we need to do dynamic threshold scaling requires body-bias modulation which is currently an expensive process in terms of IC production.
other sexy low power technologies: adiabatic logic (charge recovery), and asynchronous logic (the majority of power is consumed by the clock so let's get rid of it).
most of /. supports Ron Paul. the IT industry's productivity and Ron Paul search traffic are inversely correlated.
and it is natural that engineers should support paul: he's obviously the socrates of this election. engineers are used to hearing someone assert "XXX is not possible" and declaring that indeed "XXX is possible." Ergo Ron Paul. the "subvert the dominant paradigm" candidate '08
Ron Paul's candidacy is a lesson in self-fulfillment: he cannot win because there are not enough engineers willing to convince you that he can win. And since he can't win, he must be bat-shit crazy for trying. And then there's the wacky supporters that drink a little too much bongwater-kool-ade. Libertarianism was cooler when it wasn't being made fun of cuz of the hippies.
Mostly, I think haters are just jealous that Dr. Paul is a bit of a nerd but has seen more vagina than even some dedicated porn collectors.
A lot of you seem to be missing the point and dismissing the article as system to allow designers to be lazy and release "faulty designs." The article was less about allowing bad designs and more about allow defective chips to work thereby increasing yield and product life.
Defect tolerant arrays are still not a new idea. Every single Playstation 3 that ships is assumed to have a defective SPU in it so that the Cell yield could be higher and thus the PS3 could be cheaper. FPGAs are an array of finer grained processing elements and thus have lower susceptibility to defects. Many people note that FPGAs suffer a performance hit to ASICs, though an FPGA is more comparable to a CPU than an ASIC since it is a general purpose device. There are many processing tasks on which an FPGA can achieve order of magnitude higher performance than a CPU due to parallelization and I/O efficiency. Some people said that the cost of FPGAs is very high. This is simply no longer the case: the Xilinx Spartan 3E chips can implement 1M gate designs for about under 10$. Higher performance FPGAs have cost factors which are largely attributable to market demand and any economic comparison with CPUs should be normalized to account for volume. Even still, if cost/gate scales linearly one could currently devise a 1 Trillion gate FPGA for $10M based on the Spartan's costs. Even if I'm a factor of 10 off on cost, it would be the most powerful supercomputer in the world at a bargain price.
Chip defect density will increase with decreasing transistor size to a point where the most economically viable chip is a defect tolerant array that can eliminate much of the semiconductor testing and yield costs.
The major missing piece is an operating system for these things to provide a simple and transferable programming model.