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Low Voltage Is Key To Energy-Efficient Chip
An anonymous reader writes in with news from the International Solid State Circuits Conference in San Francisco of a new energy-efficient chip designed by researchers at MIT. It's said to be able to run on 1/10 the power of current chips. Texas Instruments worked with MIT on the design, which is maybe five years from production. "The key to the chip's improved energy efficiency lies in making it work at a reduced voltage level, according to... a member of the chip design project team. Most of the mobile processors today operate at about 1 volt. The requirement for MIT's new design, however, drops to 0.3 volts."
But how well does it overclock?
WHAT 9000
I see someone tagged this "noshitsherlock". But this is a hard thing to do because the difference between "0" and "0.3" is smaller than "5" lowering the immunity to upsets like noise.
That's why your cell phone has an ARM CPU and not an x86.
Engineering is the art of compromise.
aparently from the Bureau of Slowly and Painfully Working Out The Obivous.
i could live a little longer in this prison
I don't get it. As far as I know, transistor Vbe is still around 0.7V. How do they build circuits when the supply voltage is less than that? I mean, how can you fit in resistors and stuff when you have no room to drop anything?
Hmm. P=V^2/R, so dropping the voltage from 1 to 0.3 drops the power by a factor of (1/0.3)^2 ~ 10. How many MIT researchers did that take?
Well you only need to exceed Vbe (and the concept of Vbe only exists) if you have bipolar switching transistors. They're using IGFETs of some kind. I'm guessing that the way they do this is by making the channel and the gate insulation really thin, so you only need a tiny electrical field to switch it. I bet the noise immunity and rejection of external electrical and/or magnetic fields is really poor.
My work here is dung.
Er no. The CISC chips are really RISC under the hood. You need to update your knowledge. TThis isn't the 8088 era.
Will this reduction in voltage and increase in energy efficiency reduce the amount of heat generated by the chip? It would be nice to have a powerful laptop that I could actually use in my lap (without fear of roasting my dangly bits).
Great!
I'm waiting for several years now for a system that is completely silent, uses very low power and does not heat my room. And can be used and accessed all the time. And of course, one that does not make the performance penalties that VIA makes in their current EPIA offerengs (otherwise I would be there).
Fortunately this seem to be going to happen in the very near future. Chipsets and CPU's are partially powering down where ever possible, and with a flash SSD's there is no spin-up or (loud) rattling when an indexing service turns on. With voltage scaling like this, there is no need for a separate low power CPU within such a system. Screens are already powering up very quickly and OLED screens are on the horizon as well.
Who needs all those problems with hibernate and suspend if your system is on all the time, while staying below a few volts?
Good, I'm switching off my main computer now, I cannot sleep with the fans and hard disk rattling away. I'll have to read the replies tomorrow after powering up for a few minutes (sleep & hibernate are broken due to some peripherals).
They've even managed to make 1/10=0.3
To each, mine.
I guess they just figured out what the industry has known for years. Doesn't anyone notice that voltage requirements have been going down as power goes down?
Athiesm is a religion like not collecting stamps is a hobby.
If they can just get this thing down to zero volts, this chip will run forever!
Power is equal to the voltage multiplied by the current, so if the current stays the same and the voltage drops to 1/3, well, so does the power.
(Yes, I'm well aware that's only ohmic power, so shoot me.)
It's very simplistic to say that with voltage drops comes power efficiency - process geometry and materials play a part here too (and I'm not even going to mention the issues with noise tolerance and problems with SSO - Simultaneous Switching Outputs at the 0.3v level). So called 'current' (90nm) geoms are a nightmare for power leakage due to the the relatively small atom thickness that goes to make the gate of the switching transistors. You need to look at such tricks as gate oxides and other power mitigating technologies... BTW - When I say 90nm is current, I know people are doing 65nm, 45nm, 32nm and beyond (which are, given process geometry/power efficiency/newer techniques slightly better in some ways) but the lower geoms are slightly ahead of the curve somewhat..
subthreshold circuits with dynamic voltage scaling are fun and stuff, but the real issue at small geometries is leakage currents which constitute the majority of power consumption. Traditional dynamic voltage scaling doesn't help much because leakage is dominated by the threshold voltage not the power rail. multi-threshold CMOS uses enable signals to turn on and off high leakage paths. this does not help with active mode leakage when the system does not need to operate at full speed. to reduce active mode leakage we need to do dynamic threshold scaling requires body-bias modulation which is currently an expensive process in terms of IC production.
other sexy low power technologies: adiabatic logic (charge recovery), and asynchronous logic (the majority of power is consumed by the clock so let's get rid of it).
Sure some CISCs have a RISC under the hood, but that just means you need to have a "virtual machine" that emulates a CISC on top of the RISC. Those extra layers mean more internal operations which mean more switching.
Engineering is the art of compromise.
Can you please put a link in the sidebar that does the equivalent of showing every comment in full format? I am sick of having to click the "x more" link, wait a few seconds for it to load, click the link again and wait, click and wait, click and wait, click and wait. I like to browse through all the comments, and making me work for up to 2 minutes with ajax requests is annoying as hell.
Please, please give us a "all comments" link. If I still have to drag the bar to "Full" after doing so, that is fine. But honestly, I'm getting tired of clicking and waiting within every article just so I can read the comments.
Funny how I learned that without spending $40K a year to go to a Cambridge school.
There have been 150-200mV microcontrollers (pdf) at the University of Michigan for some time now: http://wimserc.org/research_highlights/Submiminal_Processor_Research_Highlight.pdf Conference paper 3: http://vlsida.eecs.umich.edu/resource.php?grp=1 what is new is TI and MIT are involved in a commercial low voltage product. But thats still 5 years out. MIT is good at getting press.
Power consumption in a digital circuit can be approximated by the formula:
Pavg = N*f*C*Vdd^2 + Pleak
where N is the probability of a gate switching during one clock cycle, f is the clock frequency, C is the average gate capacitance, Vdd is the supply voltage, and Pleak is the power loss due to current leakage. Since power is proportional to the square of the voltage but directly proportional to everything else, reducing the voltage has a much greater impact on total power consumption. Going from 1V to 0.3V implies a >10x dynamic power reduction.
Visit the
Why do overclockers have to ruin everything? Who gives a crap? Buy the chip and save some money from low power usage. It's obviously not engineered for overclocking so go out and rice out a Civic instead because it's the same damn thing. And yes. I just made a car analogy. There ya go.
The more voltage the more power, old computers and logic used 5V, 0.3V will be very hard to use because noise in the computer and in chips may reach 0.15 Volts, the absolute minimum resolution for the circuitry to distinguish between high and low voltage at 0.3 volts.
Researchers have proved that the secret to longevity is to continue to live without dying.
Enlightenment? It's just a flush in the pan.
TFA isn't very techincal, and makes it sound like the MIT team isn't doing anything very interesting (they mention 8-transistor SRAM cells, but even regular CPUs sometimes have to use them). The interesting story here is that the chip is being operated at a voltage below the voltage where the transistors are normally viewed as being "on". In this region, transistors operate more like amplifiers than digital switches.
One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage.
Another cool thing is that the chip can actually operate at the low voltage. It's not too hard to make a chip retain state at very low voltages, but as soon as you want to do anything you usually have to raise the voltage back up before execution resumes. Any task that requires a small amount of work frequently will benefit from something like this. A contrived example of where this make a big difference is in a poorly-architected MP3 player in which the CPU has to shuffle a few thousand bytes per second to a sound chip, but in very small chunks (this poorly-architected sound chip has a very tiny buffer), hundreds of times per second. A normal chip would be constantly jumping to a high voltage and going back to sleep; depending on how long the voltage transition takes, it might have to stay in a higher voltage state constantly. This chip, on the other hand, could operate continuously at the "sleeping" voltage.
The catch is that transistors operating in the subthreshold regime are going to be pretty slow, so for any tasks that require high performance you'll have to bump the voltage back to a more normal range.
My server
Power = Current * Voltage
To reduce power consumption, you either have to reduce the voltage or the current.
If you shuffle your feet across the carpet, you'll generate static electricity at thousands of volts. The reason that this doesn't kill you is that the currents are absolutely tiny, making the power transmitted between your socks and the carpet also extremely small, and non-hazardous.
These guys are claiming that we can most effectively reduce power consumption by focusing on reducing the voltage required for the chips to run. Although you've essentially got a 50/50 chance of being correct with this claim, the reasoning behind it is far from trivial.
-- If you try to fail and succeed, which have you done? - Uli's moose
Power = Current^2 * Resistance. Reducing the voltage is good, reducing current is better since the resistance is determined by the processes and materials that make up the device.
Power = Current * Voltage
To reduce power consumption, you either have to reduce the voltage or the current.
While your formula is right, it's not too applicable for chip power usage because current is not a constant. The formula you will normally see is
P = P-switching + P-leakage
Now, P-switching = fCV^2, so you can reduce it by reducing the clock frequency, voltage, or the number of transistors. But, P-leakage actually increases exponentially as the gate threshold voltage is reduced -- so, reducing the voltage too much will not help, either. There's only so far you can go before leakage power becomes the dominant one and reducing voltage further doesn't help.
Never underestimate the bandwidth of a 747 filled with CD-ROMs.
"One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage." leakage is more dependent on threshold voltage than Vds. running a chip subthreshold means you are relying on leakage to charge up capacitance. we've had this research going on for years at MIT.
don't fuck with the boys from MIT
they can kick your ass using nothing but their brain waves from their slightly downturned head and funneled through their fingertips
laughing now, who is
Low power means great efficiency? I'm shocked to learn this!
[groan from crowd]
I'll be here all week, folks.
(if you don't know, Silverthorne is intel's next-gen low-power chip for ultra-mobile applications)
The article states it goes down to 0.3V at idle - so it doesn't actually _run_ at that voltage (just preserve register contents). Compare this to Silverthorne which has a C6 Deep Power Down State - coincidentally at 0.3V... The article also states that this cpu uses 8-bit sram cells instead of the usual 6-bit sram cells - Silverthorne also uses 8-bit sram cells for its caches.
Granted maybe this design works at even lower voltages than does silverthorne (which seems to have an operating range of 0.7V-1.0V) but if they need 5 years to get it to market it might be too late...
(I've taken the silverthorne info from http://www.heise.de/newsticker/meldung/103038, in german, but it can now or soon likely be found elsewhere)
I think a lot of people have a minor misconception of what voltage is.... that is to say they have no fucking clue what it is. The "Well DUH.... less power used = more efficient" is less accurate than it is funny when applied to voltage. It is quite possible to use the same or even more power at a lower voltage given the required amperage.
Voltage in electronics is essentially the same thing as pressure in a pipe with water being pumped through. If you have a shitty-ass leaky pipe, higher pressure causes more water to leak from the shitty-ass pipe. Now imagine you have two of these shitty-ass pipes that you want to pump an equal amount of water through. One of them has a flow restricter on the end. If you pump the same rate of water through them, the one without the restricter will have lower pressure and less water will leak from the holes in the pipe. The pressure in the other pipe, however, is higher because of the restricter. This causes increased leakage from the shitty-ass pipe and overall more water will be required to get the same amount out of the end of the pipe (and yes I realize this uses resistance to get my point across, it's impossible to describe current, voltage, or resistance without referencing another of the three so preemptive STFU). Increased pressure also increases friction, blah, blah, blah.
This basically works the same way in electronics, except instead of leaking water (at least I hope not) electronics leak heat energy. Electronics are essentially shitty-ass leaky pipes, because it's hard to build real small things (and you can quote me on that). Sure, increased voltage generally means increased overall power usage. Voltage != Power, though.
This is meant to be a simple explanation for laymen. EE's STFU, I don't want to hear about how this or that is technically wrong. It coulda been worse, I could've used cars. And no, I didn't spellcheck, reread, etc. Go to hell spelling/grammar/regular type nazi. Done.
This article seems counter intuitive. Power lines in the US are higher voltage, lower current, than local transmission lines, to reduce power loss on their primary feeds. Higher voltage means lower current, for the same power transmitted. Isn't it current passing through a resistance what causes power loss? So lowering current (and in turn raising voltage, so the power transmitted remains the same) the proper way to reduce power loss via transmission? Or am I missing something?
I work for the Department of Redundancy Department.
Embedded + Janitor = Silly Nickname.
Contrary to popular belief, voltage is *not* power. To use the analogy properly, what this article says is closer to "low horsepower key to better gas mileage". Which, while still obvious, is at least not a tautology.
It is possible for a low voltage system to transfer more energy than a high voltage one in the same amount of time if the low voltage one transfers more current (current is measured in amps, not volts). The exact relation is volts * amps = power (in watts). So if this chip ran at lower voltage but needed more amps, it could still use more power.
main(c,r){for(r=32;r;) printf(++c>31?c=!r--,"\n":c<r?" ":~c&r?" `":" #");}
From what I can remember from my Low Power VLSI class...
1. Dropping Vdd to a CMOS transistors requires you to drop the threshold voltage to maintain performance.
2. As the two voltages approach each other, theres an increase in the current in the substrate (the current which flows between n-wells in a typical CMOS transistor).
3. This substrate current ends up contributing to massive amounts of leakage current.
I couldnt resist - the handy eq. from my VLSI Design for Deep submicron book says something along the lines of
Isubstrate =u0*cox*(w/l)*Vt^2 *e^((Vgs-Vth )/n*Vt)
u0 : carrier mobility
Cox: gate oxide cap
w&l: transistor dimensions
Vt : thermal voltage
n : some tech parameter
Vgs: Voltage between Gate and Source
Vth: Threshold Voltage
Just make a dual core CPU, and have one core run on +5 volts, and the other on -5.
I'd have to read the paper to know for sure, but I'd think they'd have to do some fundamental device process work to make a chip work at that low of a supply voltage. The threshold voltage (or "turn-on voltage" as some people call it) of a transistor doesn't scale with reducing device size, although there are steps that can be taken to adjust the threshold voltage in process, like ion implantation of various types. It's either that or they're operating it in subthreshold. The only problem with subthreshold operation is that it's incredibly slow. I guess it's conceivable though, for low-power, low-intensity applications where speed isn't a factor.
Let's assume they when with adjusting the threshold voltage. In order to make a low threshold voltage possible and practical, you'd have to be able to set the threshold voltage very precisely over process and temperature, etc, or else you'd get a zero or negative threshold voltage, resulting in an depletion-mode transistor (google it) that was always on, which wouldn't exactly be good for power consumption.
On a different note, it seems they use an integrated DC-DC converter to adjust the transistor supply voltage seen by the transistors on the fly. DC-DC conversion reduces the efficiency of a circuit, but 90%+ efficient switching converters are available, and for an ninefold increase in efficiency, that would be worth it. Unfortunately, switching regulators are also noisy. The little spikes caused by a buck or buck-boost converter could conceivably cause some of the transistors to unpredictably flip, especially if they're operating at such a low supply voltage.
Apparently they've solved all these issues, if it made it to ISSCC. ISSCC is the big leagues of circuit - they don't let snake oil or unproven claims in.
You are correct about power lines. The high voltage / low current reduces power lost due to the resistance of the wires. When you're dealing with long pieces of wire, the resistance adds up. Integrated circuits, however, are very small and though they are made of semiconductors (which are generally more resistive than metals) resistive losses aren't the big concern. In a semiconductor the important things are electric fields and charges moving about. Making a transistor work at low voltage means there are smaller potential barriers involved for charges to cross.
Basically, anyway.
1/10 = 0.3
Power tends to be proportional to fCV^2, yes. But the achievable clock frequency f is actualy a function of V. Higher voltages = lower gate delay = higher freq, as many overclockers have discovered. So power tends to scale with V^3. (Assuming you are getting the optimal performance out of your process technology. I mean you could increase V and not take advantage of the bonus in f and only use ~V^2 more power, or decrease f wihtout decreasing V to use ~V less power, but that would mean you were wasting power for equivalent performance.) I've ignored where V gets small and static power starts to dominate dynamic power.
"You saved 1968." - Ms. Valerie Pringle to the crew of Apollo 8
Gas mileage is found to be a key factor in automobile efficiency......
I am the unwilling control for my Origin.
And the ultimate in energy efficiency is ... the 0 Volt processor
...
Yes, this marvel of technology will be completely silent, generate no heat whatsoever and emit no electromagnetic radiation at all. This bleeding edge device is so efficient that it requires no energy source.
The only slight stumble block we are facing in the development of this wonderful device is the difficulty in determining which bits are set at 1 and which at 0 since the electrical level for both is the same. I'm sure further research will solve this
Also, lower voltage makes for slower transistors. If I'm not mistaken, there are already plenty of microprocessors out there that can run at voltages less than 1V. It's just that they have to run much more slowly at those levels.
The voltage applied to the gate causes charged areas of the semiconductor to shift, opening a channel for current to flow. Therefore, higher voltages drive the transistors to change state faster. I'm interested in learning how slow these chips will run.
I think you're confusing threshold voltage with supply voltage. A transistor with a lower threshold voltage will leak more. That's an inherent property of the transistor depending on its dimensions and the process.
The supply voltage (which is what's being scaled) is what's put onto the end of the MOSFET's that is attached to the source. The lower this voltage, the less leakage there will be. If this voltage is 0.0001V, there will be virtually no leakage as the transistor is pretty much powered down.
For a typical CMOS digital circuit, Vds will also be Vgs as far as I'm aware. So lowering supply voltage will decrease leakage.
the CPUs may consume less power, but it'll be much harder to design the power supply. not only will the voltage tolerance be much tighter, it's also much harder to design highly efficient regulators.
if you decrease a 10W CPU to 5W while the power-supply wastes an extra 3W to get there, and cost of designing such a power supply means lower reliability and higher cost, is it worth it?
Something that would help, is my NISC architecture. The Null Instruction Set Computer architecture. Not only does this architecture facilitate the lowering of the chip's voltage, you can also lower (or raise) the clock speed arbitrarily. The processor's clock speed can even be set to zero for the ultimate in power saving!
(In addition, you can increase the number of dies on a wafer, practically arbitrarily!)
I started developing the NISC architecture as an undergrad. I originally envisioned a NISC architecture as a {NOP} Instruction Set Computer. However, in an inspired moment, I realized that I could reduce the instruction set count by 1. (A savings of 100%!)