Then that's not the company he wants to work for - I'm a PhD student in computer engineering - it's not an "IT degree." Any company that would try to refer me in that direction doesn't need me - and I wouldn't need/want it. Plus I would hope that when it comes time to submit a resume he'll be applying to a particular position of group.
From what I can remember from my Low Power VLSI class...
1. Dropping Vdd to a CMOS transistors requires you to drop the threshold voltage to maintain performance. 2. As the two voltages approach each other, theres an increase in the current in the substrate (the current which flows between n-wells in a typical CMOS transistor). 3. This substrate current ends up contributing to massive amounts of leakage current.
I couldnt resist - the handy eq. from my VLSI Design for Deep submicron book says something along the lines of Isubstrate =u0*cox*(w/l)*Vt^2 *e^((Vgs-Vth )/n*Vt) u0 : carrier mobility Cox: gate oxide cap w&l: transistor dimensions Vt : thermal voltage n : some tech parameter Vgs: Voltage between Gate and Source Vth: Threshold Voltage
Then that's not the company he wants to work for - I'm a PhD student in computer engineering - it's not an "IT degree." Any company that would try to refer me in that direction doesn't need me - and I wouldn't need/want it. Plus I would hope that when it comes time to submit a resume he'll be applying to a particular position of group.
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apropos keyword
From the man page: "apropos - search the whatis database for strings"
From what I can remember from my Low Power VLSI class...
1. Dropping Vdd to a CMOS transistors requires you to drop the threshold voltage to maintain performance.
2. As the two voltages approach each other, theres an increase in the current in the substrate (the current which flows between n-wells in a typical CMOS transistor).
3. This substrate current ends up contributing to massive amounts of leakage current.
I couldnt resist - the handy eq. from my VLSI Design for Deep submicron book says something along the lines of
Isubstrate =u0*cox*(w/l)*Vt^2 *e^((Vgs-Vth )/n*Vt)
u0 : carrier mobility
Cox: gate oxide cap
w&l: transistor dimensions
Vt : thermal voltage
n : some tech parameter
Vgs: Voltage between Gate and Source
Vth: Threshold Voltage