Well unlike their CPU division the GPU division hasn't been the one bleeding massive amounts of cash, at least not until the GTX 970/980 generation from nVidia.
Their CPU division has also been bleeding people since the K8 was released. Apple has more ex-K8 employees than AMD. I have been told this this started and was primarily caused by Hector Ruiz.
Also we still have no idea how memory latency is impacted (shorter paths, but also lower clocks).
Latency is dominated by reading the DRAM itself and not the interface frequency which is why latency which is specified in clocks is roughly proportional to interface frequency.
Have you looked at the exceptions to the policy? This is no different than the new DOJ policy on civil assets forfeiture where the exceptions swallow the rule.
The FBI is not going to give up the power for their agents to testilie.
Derating is a good reason although I tend to avoid the 78L05 simply because its quiescent current is high compared to its output current. The 7805 is not much more expensive than a 78L05.
First, it states that in previous interviews (in Feb, and I'll bet the FBI has audio records to support that), he had described connecting to the network using Ethernet connected to a "Seat Electronic Box" ("SEB") which is mounted under the seats.
FBI policy is to *not* to record interrogations and instead rely on the written notes and memories of the agents. If the agent misremember or wrote down the wrong thing, then it sucks to be you.
The ADS1675 is a little weird because of all of its operating modes. The maximum data rate is 278 ksamples/second in single-cycle mode which is consistent with its settling time but in fast-response mode, the data rate of 4 Msamples/second is 10 times faster than the settling time. In wide-band mode, the data rate of 4 Msamples/second is 55 times faster than the settling time. So in its fastest modes, adjacent samples are not independent and 4 Msamples/second does not have the same meaning as it would with other converters. This is common with delta-sigma converters and why "single-cycle" or no-latency mode is a feature.
Table 2 on page 16 shows the AC noise performance which is consistent with other converters and other converter technologies; its useful AC resolution is 16 to 20 bits. The DC precision of the ADS1675 is pretty horrid compared to other "24 bit" delta-sigma converters and 20 bit converters designed for instrumentation applications but it is consistent with its AC performance.
Note that the integral nonlinearity given in the ADS1675 datasheet is measured using an optimum fit (as far as I can tell) and not end-to-end so it looks better than it really is compared to converters which specify it end-to-end. Texas Instruments sneakily leaves this fact out of the datasheet.
I remember looking at this part when it first came out. I wonder what kind of applications this thing gets used in. Ultrasound? Low IF signal processing?
I think the poster (gweihir) may be confusing delta-sigma modulator sample rate with output data rate.
Besides INL which you can often correct for with calibration, there are other things significantly limit resolution:
1 - Noise is significant and many of these converters support higher output data rates at the expense of noise which is how the same converter can support 24 bits of resolution at low data rates and 16 bits or lower at high output data rates just through configuration. Some of them may support a high data rate with low noise but the integration time to achieve that low noise makes the output data rate misleading. It is not the same as the input sample rate which is what matters for aliasing.
2 - At the high sensitivity needed for high resolution, 50/60 Hz rejection (and their harmonics) is often needed and the easy way to do that is to use a sample rate which causes an integration time which is a multiple of the 50/60 Hz cycle. That leads to a fastest sample rate of 50 or 60 samples per second or the common denominator of 10 samples per second to cover both simultaneously. 24 bit resolution often requires sample rates which are an order of magnitude slower than even this.
3 - Zero and gain drift are a problem as well. With cleverness they can be calibrated out (along with INL) but calibration at the 24 bit level is not easy. Thermocouple effects are a major problem affecting zero and temperature coefficient of resistance is a major problem affecting gain. It is worth noting that non-chopper stabilized amplifiers have limited open loop gain at this level because of *thermal* effects which cause feedback from their output stage to their input stage.
I have always wanted to design a hobby grade 6.5 to 8.5 digit multimeter but have never gotten around to it if only because of low demand. The design intricacy to get to that level is fascinating. 6.5 digits is 21 bits, 7.5 digits is 24.25 bits, and 8.5 digits is 27.5 bits.
The present Mac Mini doesn't even use an external power brick you can toss on the floor under the desk. The main case is bloated to hold the whole power supply.
While I prefer integrated power supplies they are invariably the limiting factor as far as reliability and what wears out first. If the power supply is an internal ATX format or an external power brick that allows the possibility of replacing it inexpensively; anything else is a waste of money.
By all means allow multiple levels of service. Let customers flag some traffic at their routers as high-priority which gets better latency guarantees, of course at a higher price. Then users playing games could choose to have super-low-latency connections for the stuff that matters.
This would work but the processing needed on the ISP side is not trivial and they cannot even get traffic volume reporting right although I believe that is deliberate.
I use a Phenom II 940 which is two generation and 4.5 years newer than your Opteron 165 (90nm, 65nm, 45nm) but still considered obsolete. The only application where I wish for more performance is gaming.
Flying is a pain in the ass. You need to go to an airport, get groped, wait an hour until you can board, sit in an uncomfortable seat, get fed a tiny drink if you're lucky when they want to feed it to you, use a bathroom that's tiny and uncomfortable, and wait for another 40 minutes for your luggage afterwards.
A train is just a much better experience. You can show up 2 minutes before departure, get on without a strip search, get a nice big seat, have a dining car, can get up and walk around at will, and just grab your luggage on the way out.
If it is successful then it will not be a better experience for long if TSA or competing interests like airlines have anything to say about it.
Going a little off topic, we did not need a 4th ammendment anyway:
T.S.A. officials respond that the random searches are “special needs” or “administrative searches” that are exempt from probable cause because they further the government’s need to prevent terrorist attacks.
The teams, which are typically composed of federal air marshals, explosives experts and baggage inspectors, move through crowds with bomb-sniffing dogs, randomly stop passengers and ask security questions.
No it's not. I commute a about half a dozen times a year and thought I'd try Amtrak since I'm starting from the NW corner of LA. It was neither cost nor time effective and I've no plans to take it again. Too many stops and, yes I take to take the bus part of the way back.
I agree. The L.A. to San Diego Amtrak is adequate for visiting one or the other for a day or the weekend but useless for commuting.
I suspect that the difference is that SSDs always or usually support scrubbing when powered during idle periods while various Flash memory cards and drives (USB, CF, SD, whatever) only scrub on reads and writes.
There is also a grace-period with a good-quality PSU: The SSD detects when the power is going down (like all disks do) and if the gradient is flat enough, has quite some time do get into a safe state. The OS also has at least 20ms with a good PSU, as it will keep voltages stable for that time or longer after power_good gets de-asserted. With a sane firmware design, that should be enough for the SSD to make sure no data that already was written gets corrupted (due to large sectors). Of course, with a catastrophic power-loss (crowbar over the power-rails), anything can happen, but it is not cost-efficient to prepare for that scenario.
The hold-up time after the power good signal is deasserted should be long enough however the drives do not have access to this signal. Even the operating system does not have access to this signal on a normal desktop computer because it results in the equivalent of a hardware reset.
There is more going on with Flash based drives which makes power loss during writes more dangerous than with rotating media. Besides the risk of corruption to the Flash drive's metadata including the sector translation table which can render the drive completely inoperable, the Flash chips themselves can operate unpredictably if power is lost during a write.
If the risk was only to pending writes, then Flash drives would be no worse off than rotating media.
The power loss problem with SSDs is actually much worse than with rotating storage extending past just losing recently written data. Every write to a SSD including garbage collection requires manipulation of the sector translation table and if *that* becomes corrupted, then the drive will usually become inaccessible. The power loss protection is needed more to protect the drive's metadata than pending written data. If the SSD *only* lost the most recently written data, then there would not be a problem.
It amazes me the number of devs I've worked with over the years who just could not understand that write order isn't necessarily preserved across crashes (or even restores from backups), and being clever with "I wait for the write of A to finish before I write B, so there can never be a B without its A" is wishful thinking.
Drives support some form of write barrier which is suppose to allow this but of course many drives, rotating and solid state, lie about completed writes in the quest for better benchmark scores.
I have exhausted UV erasable EPROMs and UV erasable EPROM based microcontrollers but never a Flash based one.
While cell size and the number of bits per cell matters for the number of program and erase cycles and retention, the type of Flash memory also matters. NAND Flash suffers from significant read (and write) disturbance which is much less of a problem with EPROM, EEPROM, or NOR Flash.
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Their CPU division has also been bleeding people since the K8 was released. Apple has more ex-K8 employees than AMD. I have been told this this started and was primarily caused by Hector Ruiz.
Latency is dominated by reading the DRAM itself and not the interface frequency which is why latency which is specified in clocks is roughly proportional to interface frequency.
Have you looked at the exceptions to the policy? This is no different than the new DOJ policy on civil assets forfeiture where the exceptions swallow the rule.
The FBI is not going to give up the power for their agents to testilie.
Derating is a good reason although I tend to avoid the 78L05 simply because its quiescent current is high compared to its output current. The 7805 is not much more expensive than a 78L05.
That is a recent change and the DOJ says lots of things. I am sure the FBI has a way to weasel out of it.
FBI policy is to *not* to record interrogations and instead rely on the written notes and memories of the agents. If the agent misremember or wrote down the wrong thing, then it sucks to be you.
Lawyers. Then we can get down to the business of building something to save us.
That is the second half of Protector with Bussard Ramjet based warships and minimum ranges of light minutes.
The Gripping Hand and Footfall come to mind as other Niven books with relatively realistic space battles and they do not involve relativistic speeds.
The ADS1675 is a little weird because of all of its operating modes. The maximum data rate is 278 ksamples/second in single-cycle mode which is consistent with its settling time but in fast-response mode, the data rate of 4 Msamples/second is 10 times faster than the settling time. In wide-band mode, the data rate of 4 Msamples/second is 55 times faster than the settling time. So in its fastest modes, adjacent samples are not independent and 4 Msamples/second does not have the same meaning as it would with other converters. This is common with delta-sigma converters and why "single-cycle" or no-latency mode is a feature.
Table 2 on page 16 shows the AC noise performance which is consistent with other converters and other converter technologies; its useful AC resolution is 16 to 20 bits. The DC precision of the ADS1675 is pretty horrid compared to other "24 bit" delta-sigma converters and 20 bit converters designed for instrumentation applications but it is consistent with its AC performance.
Note that the integral nonlinearity given in the ADS1675 datasheet is measured using an optimum fit (as far as I can tell) and not end-to-end so it looks better than it really is compared to converters which specify it end-to-end. Texas Instruments sneakily leaves this fact out of the datasheet.
I remember looking at this part when it first came out. I wonder what kind of applications this thing gets used in. Ultrasound? Low IF signal processing?
I think the poster (gweihir) may be confusing delta-sigma modulator sample rate with output data rate.
Besides INL which you can often correct for with calibration, there are other things significantly limit resolution:
1 - Noise is significant and many of these converters support higher output data rates at the expense of noise which is how the same converter can support 24 bits of resolution at low data rates and 16 bits or lower at high output data rates just through configuration. Some of them may support a high data rate with low noise but the integration time to achieve that low noise makes the output data rate misleading. It is not the same as the input sample rate which is what matters for aliasing.
2 - At the high sensitivity needed for high resolution, 50/60 Hz rejection (and their harmonics) is often needed and the easy way to do that is to use a sample rate which causes an integration time which is a multiple of the 50/60 Hz cycle. That leads to a fastest sample rate of 50 or 60 samples per second or the common denominator of 10 samples per second to cover both simultaneously. 24 bit resolution often requires sample rates which are an order of magnitude slower than even this.
3 - Zero and gain drift are a problem as well. With cleverness they can be calibrated out (along with INL) but calibration at the 24 bit level is not easy. Thermocouple effects are a major problem affecting zero and temperature coefficient of resistance is a major problem affecting gain. It is worth noting that non-chopper stabilized amplifiers have limited open loop gain at this level because of *thermal* effects which cause feedback from their output stage to their input stage.
I have always wanted to design a hobby grade 6.5 to 8.5 digit multimeter but have never gotten around to it if only because of low demand. The design intricacy to get to that level is fascinating. 6.5 digits is 21 bits, 7.5 digits is 24.25 bits, and 8.5 digits is 27.5 bits.
While I prefer integrated power supplies they are invariably the limiting factor as far as reliability and what wears out first. If the power supply is an internal ATX format or an external power brick that allows the possibility of replacing it inexpensively; anything else is a waste of money.
So systemd caused the rail crash? I knew it!
If rail becomes a serious threat to the airlines then that will change. TSA already practices molesting rail passengers on a trial basis.
The business model is finding Sara Connor.
This would work but the processing needed on the ISP side is not trivial and they cannot even get traffic volume reporting right although I believe that is deliberate.
I use a Phenom II 940 which is two generation and 4.5 years newer than your Opteron 165 (90nm, 65nm, 45nm) but still considered obsolete. The only application where I wish for more performance is gaming.
If it is successful then it will not be a better experience for long if TSA or competing interests like airlines have anything to say about it.
Going a little off topic, we did not need a 4th ammendment anyway:
T.S.A. officials respond that the random searches are “special needs” or “administrative searches” that are exempt from probable cause because they further the government’s need to prevent terrorist attacks.
The teams, which are typically composed of federal air marshals, explosives experts and baggage inspectors, move through crowds with bomb-sniffing dogs, randomly stop passengers and ask security questions.
http://www.nytimes.com/2013/08...
I agree. The L.A. to San Diego Amtrak is adequate for visiting one or the other for a day or the weekend but useless for commuting.
I suspect that the difference is that SSDs always or usually support scrubbing when powered during idle periods while various Flash memory cards and drives (USB, CF, SD, whatever) only scrub on reads and writes.
Older Flash memory is fabricated using larger process sizes leading to longer retention.
My own experience with USB Flash drives is that even when new, they had a powered and unpowered retention of less than a year.
The hold-up time after the power good signal is deasserted should be long enough however the drives do not have access to this signal. Even the operating system does not have access to this signal on a normal desktop computer because it results in the equivalent of a hardware reset.
There is more going on with Flash based drives which makes power loss during writes more dangerous than with rotating media. Besides the risk of corruption to the Flash drive's metadata including the sector translation table which can render the drive completely inoperable, the Flash chips themselves can operate unpredictably if power is lost during a write.
If the risk was only to pending writes, then Flash drives would be no worse off than rotating media.
The power loss problem with SSDs is actually much worse than with rotating storage extending past just losing recently written data. Every write to a SSD including garbage collection requires manipulation of the sector translation table and if *that* becomes corrupted, then the drive will usually become inaccessible. The power loss protection is needed more to protect the drive's metadata than pending written data. If the SSD *only* lost the most recently written data, then there would not be a problem.
Drives support some form of write barrier which is suppose to allow this but of course many drives, rotating and solid state, lie about completed writes in the quest for better benchmark scores.
I have exhausted UV erasable EPROMs and UV erasable EPROM based microcontrollers but never a Flash based one.
While cell size and the number of bits per cell matters for the number of program and erase cycles and retention, the type of Flash memory also matters. NAND Flash suffers from significant read (and write) disturbance which is much less of a problem with EPROM, EEPROM, or NOR Flash.