A godsend wouldn't be so damn butt ugly.
I didn't see anywhere on that website where the player defeats Macrovision.
Also, there will be no doubt a way to do everything imaginable on the indrema. I mean no region encoding limitations, no macrovision (cross fingers), mp3 disk playing, sega emulators, new emulators, arcade emulators, gameboy emulators, psx emulators, etc.
Of course the emulators will be do-it-yourself emulators of course, but who cares.
That is a godsend. This is an ugly piece of crap. Of course that assumes it even exists.
The important thing to realize here is that the best support you will have for specific hardware platforms will be provided with standard libraries. It's not as if you will be performing some sort of if/then/else construct and the compiler will swap it for some SSE operation. The SSE operations (like 3dnow) are only useful for some very specific algorithms that would otherwise bring your GPU to a crawl.
What really happens is that you might want to perform some image manipulation or motion compensaion or some mpeg-2 encoding, etc. You would then call a primitive that would have been provided by the hardware vendor. The compiler would likely have little to no knowledge of what you are doing.
Libraries like direct3d and similar will use these primitives and further distance you from the hardware.
The "optimizing compiler" could provide you a template with which you can directly use the special instructions if you know enough about your algorithm to be able to effectively use them. Without this very specific guidance, it is very unlikely that a compiler will be able to take advantage of the instructions. Likewise, it is extremely unlikely that average joe programmer (and that includes about 99% of the programmers out there) will ever see the need to use them or will understand enough about what the algorithms they use to be able to use them as effectively as the primitives that the vendors provide.
gcc supporters will easily be able to extract the primitives from those libraries provided by Intel and amd. Furthermore, with Intel's recent support of FSF and similar efforts, I don't think any of us will need to worry about whether there will be support for SSE2.
I don't think we're talking about defects that are detected when the memory is in the wafer stage. I think we are talking about the die that passed the initial wafer probe and then were packaged and then fail somehow at or after the packaging or even shipping stages.
We are talking about packaged silicon here. And we're talking about populated DIMM/SIMM/etc boards that fail. There's no way in hell that a manufacturer would let faulty die get that far, and by that time, there's no way that any type of depositing or fib technique is gonna be practical in any way at this point.
so with that in mind, let's return to the topic they are talking about. Why don't you just allow us to think that is't really cool to use software to lock out blocks of RAM? (i.e. by using page protection that is already present in the OS and already supported by the CPU)
So in conclusion, I think there are plenty of us at./ that have a clue about memories, memory protection architecture, fabrication, production, and testing techniques. We also are aware that there are a few techniques in practice like the one that you mention, but I seriously doubt that they are applicable to such dense cells as memories. Even if you could spare the silicon real estate and added logic and routing to provide the redundant resources, you would still have to reroute on a per-die and per-failure basis. And that assumes that the defect belongs to a special class of failures and is confined to an easilty fixable range of memories, etc.
Hell, either do I! And why is that, well it's because the Win95 you had on your P166 was quite shitty and the Win98SE you (and your father) are running on K6-2 is quite more reliable. Plus, DirectX and 3d and other software compatibility sucked back in the days of P166, and are much better now, explaining why your games work well now.
verdict: your problems were caused by software, i.e. your post is off-topic.
mega
Let me guess: you are a software programmer and have no hardware knowledge. Maybe you should hop on over to MDR and take a look at their P4 architectural preview. It's pretty good and it's in laymen terms, so you might be able to grasp the completely different pipeline and architecture that the P4 will have compared to the P3. On the other hand, I haven't seen an equivalently basic review of a P3 or before, so you probably won't have much to compare against.
Nevermind. Just go on continuing to believe that the pentium4 is very similar to the pentium3 if only because Intel only bothered to change 7 or the 8 characters in the name.
ok, so why didn't Intel release a 200 MHz 64-bit pentium2 back in 1995? Well, let's see... there was no need for a 64-bit architecture back in 1995!! Who the hell would have paid a fortune to have it? Certainly not the consumer market. Hell, workstations weren't even 64-bit yet 5 years ago.
Oh yeah, and then there's brand recognition. Oh yeah, and then there's fab capacity. And then there's the problem of getting vendors to purchase their products (i.e. some vendors still won't populate boards with AMD parts!)
Then of course there's that cost aspect. There's no way Sun can get their cost down -- it's all about volume here. Intel and AMD can sell their 64-bit architecture to consumers eventually since they already have that business model worked out. Then you are making big assumptions that people want to drop legacy support, whether they can afford to or not. Then not running Windows will be hard to minimize. As much as I'd like the world's most popular OS's to all be *nix-based, I just don't see it happening. Heck, well over half the engineering grads in the world don't know flip about unix when they get their BS's.
Sun would have to play their cards wayyyyyyyyyyyy right to take any market share at all. There's no chance AMD and Intel will be caught with their pants around their ankles. I'd say you were definitely smoking something strong. If Sun wanted to make a viable play into the server market, they should have done it by now. They've had 64-bit datapaths for some time now. Waiting until the competition has comparable architectures is missing an important window.
If I only had a nickel for all the morons who ask this question every time an Intel article is posted here...
Let's see. I could probably use it to encode DVDs into CDROM size with divx. I could use it to decode divx and watch my DVDs. Yeah, today's higher-end PCs do this quite nicely, however DVDs and divx encoding are today's technology. There will be more CPU intensive technology tomorrow.
Likewise, there will be people with 667-MHz P3s who will want to upgrade in a few more years. They'll obviously want something a couple times faster than what they already have or they won't see the speedup they want. And if there are 2GHz platforms out there, that means that the 1.667 GHz platforms will be much more affordable for them. And who in their right mind would complain about getting a very fast machine at a low price?
If we all haven't figured it out by now, the presence of a high-end market makes everything more affordable to the remainder (probably 95%) of the market. With that in mind, I don't know what the hell people with a half a brain can possibly be bitching about when they hear about the 2GHz boxes on the horizon.
I got a 1GHz P3 box from Dell with the 10% discount and a 2-week time to get to my doorstep. Cost me about $2k with lotsa cool stuff and a 19" monitor.
From the referenced article: Intel and HardOCP have recently struck up a relationship that somehow involves folks other than lawyers for a change. They were kind enough to send us their new Pentium III 1.13GHz CPU to test. Along with that, they sent an Intel VC820 (i820 chipset) mainboard and some RAMBUS. Basically, they sent a computer in a box except for the hard drive. They asked us to test their 1.13GHz part on the i820 platform. Seemed like a no-brainer to me (perfect for us). Well it did not turn out that way
Yeah, Intel approached you and requested politely, "Please test our chip on our motherboard." Hahah, sounds innocent enough. Hahaha... there's one more anti-Intel site I won't be spending my idle moments visiting.
Well, it sounds like it has the viability of DIVX.
The best way to prevent such an unbelievable trend is not to buy into it -- even if the exclusive copyright is to the passworded publisher.
Simple capitalism will ensure that there will be a competing (although not interchangeable) work of literature that will be distributed under another medium.
IMO, the most enlightened writers will not allow their work to be distributed under such a restrictive agreement.
Either way, I'm not even sure that this means of distribution will even yield more revenue.
Dude. The article was about P-O-W-E-R C-O-N-S-U-M-P-T-I-O-N. Yes, Toshiba was bashing Transmeta for a failure to deliver on expectations.
Most of the TM bashing I've ever heard is that they use completely contrived benchmarks that put little-to-no load on their chip to fabricate these completely ridiculous power numbers so they look great against Intel and AMD.
Then of course they neglect to say that in the low-power notebook market, the CPU only consumes about 25% of the power. So even if they reduce their power consumption to 0, they could only improve battery life by 33%.
I think you are misinterpreting the arguments. People seem to me to be saying they don't want to take a serious performance hit if all they are getting in return is a small power savings.
That would be because the M$ chip is not an Intel competitor (x86) and thusly won't appear in IBM compatible computers.
Re:Looks like buying the StrongARM team is paying
on
2Ghz P4 Shown Off
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· Score: 1
What I do take issue with is this 850mW figure for a 500MHz PIII. Intel's low power consumption tricks up till now have involved idling the processor when there isn't much happening, and I strongly suspect that this 850mW figure has a lot of idling in its measurement time frame. That figure of 5.5W max looks far more likely to really reflect the power consumption of the low power PIII.
Um... duh? I believe it was clearly spoken that the 850mW figure was taken during a typical office application. I don't remember the numbers offhand, but something like a computer uses as little as 10% of its resources during a typical office application since it can take a quick nap between virtually every one of the user's keystrokes. It should then not be surprising that they can get the power figure to less than a watt during typical office applications.
but I do wish that Intel would be more 'honest' with its figures. The fact that they included peak power consumption seems to me to be more honest than, say, Transmeta has been in their marketing strategies.
I was at the EPF where Transmeta had a large amount of presence. Their power measurements were all made during these "sleepy" office applications, and they always compared against the P3's peak power consumption, with no power saving features on. And you think Intel's been misleading you?
Of course it was a handpicked chip! It was a P4 sample you moron. What, you think they were going to randomly pull a chip off the line and bring it to the forum untested?
The fact that it *can* be overclocked by 25% to run at 2GHz at room temperature they said is pretty amazing if you ask me.
Yeah, it was a friggin demo. Yeah, the article wasn't all that specific. It was a msnbc article not a journal article. What exactly do you want?
For all you lameass non-powerusers out there: Ok, maybe you don't need a 2GHz chip to run Netscape, Notepad and Acroread. But I'm sure you frugal jerkoffs can appreciate a cheaper 500MHz celeron so you can edit text faster. If you didn't realize it, the competition in the high performance has an astonishing effect on the low performance market. The mere existence of the 1.4GHz P4 will seriously reduce the price of the sub 1GHZ P3 boards. Unfortunately in this case, your ignorance is not bliss.
What are you talking about? Have you any idea what it means to divide a pipeline into more stages? If you simply divide a pipeline into 2x the stages, you will of course now accomplish the same amount of work in twice the number of stages. That means half the work per stage. Duhhh. You can still commit one instruction per clock, meaning that barring changes of flow, you haven't affected your performance per clock tick. Of course now you can up your clock frequency, meaning that now you can increase your performance per second.
By your reasoning, everyone should make single-cycled "pipes" that can execute an entire instruction in a single cycle rather than simply 1/12 of an instruction per stage. The only problem is that now your clock speed is slow as hell. Either way, you still only commit one instruction per cycle.
I think you might want to finish your 2nd computer architecture class before you comment any further. I know we would all appreciate it as well.
Wow, I'm surprised you had all that much experience hand-coding assembly on the Merced. It's not that common that I meet people that aren't in the compiler business that get to do that;)
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A godsend wouldn't be so damn butt ugly. I didn't see anywhere on that website where the player defeats Macrovision. Also, there will be no doubt a way to do everything imaginable on the indrema. I mean no region encoding limitations, no macrovision (cross fingers), mp3 disk playing, sega emulators, new emulators, arcade emulators, gameboy emulators, psx emulators, etc. Of course the emulators will be do-it-yourself emulators of course, but who cares. That is a godsend. This is an ugly piece of crap. Of course that assumes it even exists.
What really happens is that you might want to perform some image manipulation or motion compensaion or some mpeg-2 encoding, etc. You would then call a primitive that would have been provided by the hardware vendor. The compiler would likely have little to no knowledge of what you are doing.
Libraries like direct3d and similar will use these primitives and further distance you from the hardware.
The "optimizing compiler" could provide you a template with which you can directly use the special instructions if you know enough about your algorithm to be able to effectively use them. Without this very specific guidance, it is very unlikely that a compiler will be able to take advantage of the instructions. Likewise, it is extremely unlikely that average joe programmer (and that includes about 99% of the programmers out there) will ever see the need to use them or will understand enough about what the algorithms they use to be able to use them as effectively as the primitives that the vendors provide.
gcc supporters will easily be able to extract the primitives from those libraries provided by Intel and amd. Furthermore, with Intel's recent support of FSF and similar efforts, I don't think any of us will need to worry about whether there will be support for SSE2.
I don't think we're talking about defects that are detected when the memory is in the wafer stage. I think we are talking about the die that passed the initial wafer probe and then were packaged and then fail somehow at or after the packaging or even shipping stages.
We are talking about packaged silicon here. And we're talking about populated DIMM/SIMM/etc boards that fail. There's no way in hell that a manufacturer would let faulty die get that far, and by that time, there's no way that any type of depositing or fib technique is gonna be practical in any way at this point.
so with that in mind, let's return to the topic they are talking about. Why don't you just allow us to think that is't really cool to use software to lock out blocks of RAM? (i.e. by using page protection that is already present in the OS and already supported by the CPU)
So in conclusion, I think there are plenty of us at ./ that have a clue about memories, memory protection architecture, fabrication, production, and testing techniques. We also are aware that there are a few techniques in practice like the one that you mention, but I seriously doubt that they are applicable to such dense cells as memories. Even if you could spare the silicon real estate and added logic and routing to provide the redundant resources, you would still have to reroute on a per-die and per-failure basis. And that assumes that the defect belongs to a special class of failures and is confined to an easilty fixable range of memories, etc.
Don't get so high on yourself over there.
Hell, either do I! And why is that, well it's because the Win95 you had on your P166 was quite shitty and the Win98SE you (and your father) are running on K6-2 is quite more reliable. Plus, DirectX and 3d and other software compatibility sucked back in the days of P166, and are much better now, explaining why your games work well now.
verdict: your problems were caused by software, i.e. your post is off-topic. mega
Nevermind. Just go on continuing to believe that the pentium4 is very similar to the pentium3 if only because Intel only bothered to change 7 or the 8 characters in the name.
ok, so why didn't Intel release a 200 MHz 64-bit pentium2 back in 1995? Well, let's see... there was no need for a 64-bit architecture back in 1995!! Who the hell would have paid a fortune to have it? Certainly not the consumer market. Hell, workstations weren't even 64-bit yet 5 years ago.
Yeah, and all three happen to not support a vast majority of the software out there. Hey what a brilliant idea!
Hmm.. That would probably be why he decided to compare it to VC++ also. D-uhhh...
Then of course there's that cost aspect. There's no way Sun can get their cost down -- it's all about volume here. Intel and AMD can sell their 64-bit architecture to consumers eventually since they already have that business model worked out. Then you are making big assumptions that people want to drop legacy support, whether they can afford to or not. Then not running Windows will be hard to minimize. As much as I'd like the world's most popular OS's to all be *nix-based, I just don't see it happening. Heck, well over half the engineering grads in the world don't know flip about unix when they get their BS's.
Sun would have to play their cards wayyyyyyyyyyyy right to take any market share at all. There's no chance AMD and Intel will be caught with their pants around their ankles. I'd say you were definitely smoking something strong. If Sun wanted to make a viable play into the server market, they should have done it by now. They've had 64-bit datapaths for some time now. Waiting until the competition has comparable architectures is missing an important window.
Let's see. I could probably use it to encode DVDs into CDROM size with divx. I could use it to decode divx and watch my DVDs. Yeah, today's higher-end PCs do this quite nicely, however DVDs and divx encoding are today's technology. There will be more CPU intensive technology tomorrow.
Likewise, there will be people with 667-MHz P3s who will want to upgrade in a few more years. They'll obviously want something a couple times faster than what they already have or they won't see the speedup they want. And if there are 2GHz platforms out there, that means that the 1.667 GHz platforms will be much more affordable for them. And who in their right mind would complain about getting a very fast machine at a low price?
If we all haven't figured it out by now, the presence of a high-end market makes everything more affordable to the remainder (probably 95%) of the market. With that in mind, I don't know what the hell people with a half a brain can possibly be bitching about when they hear about the 2GHz boxes on the horizon.
I got a 1GHz P3 box from Dell with the 10% discount and a 2-week time to get to my doorstep. Cost me about $2k with lotsa cool stuff and a 19" monitor.
From the referenced article: Intel and HardOCP have recently struck up a relationship that somehow involves folks other than lawyers for a change. They were kind enough to send us their new Pentium III 1.13GHz CPU to test. Along with that, they sent an Intel VC820 (i820 chipset) mainboard and some RAMBUS. Basically, they sent a computer in a box except for the hard drive. They asked us to test their 1.13GHz part on the i820 platform. Seemed like a no-brainer to me (perfect for us). Well it did not turn out that way
Yeah, Intel approached you and requested politely, "Please test our chip on our motherboard." Hahah, sounds innocent enough. Hahaha... there's one more anti-Intel site I won't be spending my idle moments visiting.
The best way to prevent such an unbelievable trend is not to buy into it -- even if the exclusive copyright is to the passworded publisher.
Simple capitalism will ensure that there will be a competing (although not interchangeable) work of literature that will be distributed under another medium.
IMO, the most enlightened writers will not allow their work to be distributed under such a restrictive agreement.
Either way, I'm not even sure that this means of distribution will even yield more revenue.
Most of the TM bashing I've ever heard is that they use completely contrived benchmarks that put little-to-no load on their chip to fabricate these completely ridiculous power numbers so they look great against Intel and AMD.
Then of course they neglect to say that in the low-power notebook market, the CPU only consumes about 25% of the power. So even if they reduce their power consumption to 0, they could only improve battery life by 33%.
I think you are misinterpreting the arguments. People seem to me to be saying they don't want to take a serious performance hit if all they are getting in return is a small power savings.
That would be because the M$ chip is not an Intel competitor (x86) and thusly won't appear in IBM compatible computers.
What I do take issue with is this 850mW figure for a 500MHz PIII. Intel's low power consumption tricks up till now have involved idling the processor when there isn't much happening, and I strongly suspect that this 850mW figure has a lot of idling in its measurement time frame. That figure of 5.5W max looks far more likely to really reflect the power consumption of the low power PIII. Um... duh? I believe it was clearly spoken that the 850mW figure was taken during a typical office application. I don't remember the numbers offhand, but something like a computer uses as little as 10% of its resources during a typical office application since it can take a quick nap between virtually every one of the user's keystrokes. It should then not be surprising that they can get the power figure to less than a watt during typical office applications. but I do wish that Intel would be more 'honest' with its figures. The fact that they included peak power consumption seems to me to be more honest than, say, Transmeta has been in their marketing strategies. I was at the EPF where Transmeta had a large amount of presence. Their power measurements were all made during these "sleepy" office applications, and they always compared against the P3's peak power consumption, with no power saving features on. And you think Intel's been misleading you?
Of course it was a handpicked chip! It was a P4 sample you moron. What, you think they were going to randomly pull a chip off the line and bring it to the forum untested? The fact that it *can* be overclocked by 25% to run at 2GHz at room temperature they said is pretty amazing if you ask me. Yeah, it was a friggin demo. Yeah, the article wasn't all that specific. It was a msnbc article not a journal article. What exactly do you want? For all you lameass non-powerusers out there: Ok, maybe you don't need a 2GHz chip to run Netscape, Notepad and Acroread. But I'm sure you frugal jerkoffs can appreciate a cheaper 500MHz celeron so you can edit text faster. If you didn't realize it, the competition in the high performance has an astonishing effect on the low performance market. The mere existence of the 1.4GHz P4 will seriously reduce the price of the sub 1GHZ P3 boards. Unfortunately in this case, your ignorance is not bliss.
Hmm... looks like INTC just broke an all-time high today. I hope you aren't a day trader.
By your reasoning, everyone should make single-cycled "pipes" that can execute an entire instruction in a single cycle rather than simply 1/12 of an instruction per stage. The only problem is that now your clock speed is slow as hell. Either way, you still only commit one instruction per cycle.
I think you might want to finish your 2nd computer architecture class before you comment any further. I know we would all appreciate it as well.
Wow, I'm surprised you had all that much experience hand-coding assembly on the Merced. It's not that common that I meet people that aren't in the compiler business that get to do that ;)