yeah but it will be slow and complicated. You can do it by sticking latches across a few signals and drive then using a clock.
Re:Would like to see some real-world results
on
Clockless Computing
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· Score: 2
Dirrerent methods for making async chips are available.
DIMS is 8 times bigger anc consumes 2 times more power and is 2-3 times slower. But ultra safe from power analasis attacks and fully DI meaning it will not crash if you turn the power down or bombard it with alpha rays ot damage a few transistors (a little)
Bundled data is 30% smaller to 10% bigger, consumes 10%-80% less power and runs as fast as synchronous. This is what is used in most chips.
My method (you can rtead my thesis about it) is 2 times bigger,consumes 2 times more power and gets 20-60% speen improvement over the synchronous design.
So it depends what you want, area, speed, power or security.
This is called dual-rail. I am currently implementing processors in this technology for speed. It is actually more power hungry than synchronous but a dirrerent method called bundled data is better for power.
Re:Oh yeah, how do you upgrade one of these system
on
Clockless Computing
·
· Score: 2
This is the point of asynchronous handshaking. You can do it across any speed components safely. Its request acknowledge wire pairs. Read my thesis, its a gentle inroduction to async.
The difficult was with design methodologys. Clocked is worse but easyer to design by hand. For async we use special tools which are computation hungry. PDP6 is a little too slow to desighn a async chip.
The chip decides when its ready to fetch another instruction. It times itself and it still uses pipelines, except now fine grain pipelines are much cheaper and faster. You dont just wait for a finite period of time. The operation that you are executing will signal that its ready to move onto the next pipeline stage and the prevous stage is ready to accept another piece of data.
Re:The problem with overcooling async logic
on
Clockless Computing
·
· Score: 2
You are confusing asynchronous logic with wave pipelining systems. We still need controll units. There are two methods. Eather you do things in DI where nothing can break the chip as every gate transition is acknowledged so even it a gate takes a year to switch it will still complete its operation. The second is using delay components which are placed amongst the datapath so it the datapath heats up so does the delay line. Its much safer than synchronous where if you do dump the chip into -100c its gates can out run the clock and alter the next latch during the clock strike.
Although we say its self timed so operations can take different ammounts of time there is still a hard upper bound of worst case operations. Async circuits have been used in all sorts of hard delay systems like dynamicly vareable depth fifo in CD players or 1GHz+ FIR filters on hard disk reads.
You can make anything in async that you make in sync.
Re:Arbiters... Something doesn't make sense.
on
Clockless Computing
·
· Score: 2
Correct! Fantastic! Someone on slashdot asked a question about async and another person answeared it correctly! The fact that the arbiter can take an infinite ammount of time is talked about a lot but never happens. Sometimes if you have two requests which just hit the border than it can take a ns for the unit to balance. This will happen once every year. For a longer period of time like 1 ms you would have to wait will the end of the universe. As engineers we dont plan our products to last that long and even if it happens then there is no fault as its self timed.
Imagine working in async and once every 2 years someone on slashdot posts a message about async. Then 1000 slahsdotees who dont get out much and think theire experts about hardware will say something like "How do you tell the time?". Their descussions continue untill they conclude between themselves that you cannot ever be sure if a register has returned back to the regbank and it will never work. Ah well. BAck to work heh?
If you design your async system correctly then you will NEVER be slower than the clock estimation of time required for an operation. Read my paper at my site about direct translation.
yep but you dont have to make each stage equal in time. so logical operaions happen faster and difficult arithmetic operations (e.g. 1-1) as fast as synchronous.
Well NCL or "4 phase return to zero one of n codes" was invented by Muller in 1958. Theseus might act like they invented async but people were doing dual rail well before they came along.
Their only comtribution is trying to use threshold "gates" (with hysteresis) which might be very nice isn't usefull for anyrthing except for adders. Their implementations use DIMS gates (again from 1958) and when they dont they have a non DI (Delay Insensitive) implementation with orphan hazards.
I am doing research on simmilar systems and have found their buziness stratergy to make patents well after they were invented and then make every one beleive that they invented it. They do have some very nice mind melting presentations (Im guessing you went to one).
Sorry I didnt post these sooner but I am at a asynchronous computing workshop. If you are intrested in async then here is a list of cool websites: Async home is the main website with resources events and background. Amulet group have a selection of resources and news. And if you want a laugh then check out rat powered cpus
To aveclock an asynchronous cpu you spray it with CFC. We have a couple in the office and its cool to see them speed up. Or you can attach a faster hamster.
I have written a paper and am writing my thesis on synchronous to asynchronous conversion. You simply write your design in vhdl/verilog/schematics and you get a self timed design out. I placed a mips processor through it and it was about 30% faster.
Ive had replies like: We dont want to allow non standard browsers as the 1% of the poeple using them will send us bug reports about some pages not working. Its easyer to tell them to go away.
When I find that a website doesnt work with Linux or my browser then I send them an email. Often they just ignore them but for examle the inquirer just this morning corrected their site after I emailed to the webmaster on friday with the bug.
What should I make next?
on
Lego Trebuchet
·
· Score: 3, Interesting
As a buzy research student currently writing his thesis I have no time to sit about and play with LEGO all day. Oh wait no. Thats what I do all day every day while avoiding work. Anyway after making a internet controllable camera and an internet controllable robot, I have run out of inspiration. The research group lego has two motors and I want to make something that people can control over the internet. Any suggestions?
Slashdot Mirror
yeah but it will be slow and complicated.
You can do it by sticking latches across a few signals and drive then using a clock.
Dirrerent methods for making async chips are available.
,consumes 2 times more power and gets 20-60% speen improvement over the synchronous design.
DIMS is 8 times bigger anc consumes 2 times more power and is 2-3 times slower. But ultra safe from power analasis attacks and fully DI meaning it will not crash if you turn the power down or bombard it with alpha rays ot damage a few transistors (a little)
Bundled data is 30% smaller to 10% bigger, consumes 10%-80% less power and runs as fast as synchronous. This is what is used in most chips.
My method (you can rtead my thesis about it) is 2 times bigger
So it depends what you want, area, speed, power or security.
This is called dual-rail. I am currently implementing processors in this technology for speed. It is actually more power hungry than synchronous but a dirrerent method called bundled data is better for power.
This is the point of asynchronous handshaking. You can do it across any speed components safely. Its request acknowledge wire pairs. Read my thesis, its a gentle inroduction to async.
The difficult was with design methodologys. Clocked is worse but easyer to design by hand. For async we use special tools which are computation hungry. PDP6 is a little too slow to desighn a async chip.
The chip decides when its ready to fetch another instruction. It times itself and it still uses pipelines, except now fine grain pipelines are much cheaper and faster. You dont just wait for a finite period of time. The operation that you are executing will signal that its ready to move onto the next pipeline stage and the prevous stage is ready to accept another piece of data.
You are confusing asynchronous logic with wave pipelining systems. We still need controll units.
There are two methods. Eather you do things in DI where nothing can break the chip as every gate transition is acknowledged so even it a gate takes a year to switch it will still complete its operation.
The second is using delay components which are placed amongst the datapath so it the datapath heats up so does the delay line.
Its much safer than synchronous where if you do dump the chip into -100c its gates can out run the clock and alter the next latch during the clock strike.
Although we say its self timed so operations can take different ammounts of time there is still a hard upper bound of worst case operations.
Async circuits have been used in all sorts of hard delay systems like dynamicly vareable depth fifo in CD players or 1GHz+ FIR filters on hard disk reads.
You can make anything in async that you make in sync.
Correct! Fantastic! Someone on slashdot asked a question about async and another person answeared it correctly!
The fact that the arbiter can take an infinite ammount of time is talked about a lot but never happens. Sometimes if you have two requests which just hit the border than it can take a ns for the unit to balance. This will happen once every year. For a longer period of time like 1 ms you would have to wait will the end of the universe. As engineers we dont plan our products to last that long and even if it happens then there is no fault as its self timed.
Imagine working in async and once every 2 years someone on slashdot posts a message about async. Then 1000 slahsdotees who dont get out much and think theire experts about hardware will say something like "How do you tell the time?".
Their descussions continue untill they conclude between themselves that you cannot ever be sure if a register has returned back to the regbank and it will never work.
Ah well. BAck to work heh?
If you design your async system correctly then you will NEVER be slower than the clock estimation of time required for an operation. Read my paper at my site about direct translation.
yep but you dont have to make each stage equal in time. so logical operaions happen faster and difficult arithmetic operations (e.g. 1-1) as fast as synchronous.
on my website read my paper im writing. It explains how async pipelines are very easy, fast and low power etc.
Well NCL or "4 phase return to zero one of n codes" was invented by Muller in 1958. Theseus might act like they invented async but people were doing dual rail well before they came along.
Their only comtribution is trying to use threshold "gates" (with hysteresis) which might be very nice isn't usefull for anyrthing except for adders.
Their implementations use DIMS gates (again from 1958) and when they dont they have a non DI (Delay Insensitive) implementation with orphan hazards.
I am doing research on simmilar systems and have found their buziness stratergy to make patents well after they were invented and then make every one beleive that they invented it. They do have some very nice mind melting presentations (Im guessing you went to one).
You guess. It will take x ammount of time for an average y instruction. The data dependantness is a small effect.
Sorry I didnt post these sooner but I am at a asynchronous computing workshop.
If you are intrested in async then here is a list of cool websites:
Async home is the main website with resources events and background.
Amulet group have a selection of resources and news.
And if you want a laugh then check out rat powered cpus
The idea comes from a paper in 1958. Several machines in the 60/70s were asynchronous including the MU5 which in its day was the fastest around.
To aveclock an asynchronous cpu you spray it with CFC. We have a couple in the office and its cool to see them speed up.
Or you can attach a faster hamster.
I have written a paper and am writing my thesis on synchronous to asynchronous conversion. You simply write your design in vhdl/verilog/schematics and you get a self timed design out. I placed a mips processor through it and it was about 30% faster.
This might be because theseus have no novel stuff. They copied all their work from a paper by muller from 1958.
Ive had replies like:
We dont want to allow non standard browsers as the 1% of the poeple using them will send us bug reports about some pages not working.
Its easyer to tell them to go away.
When I find that a website doesnt work with Linux or my browser then I send them an email.
Often they just ignore them but for examle the inquirer just this morning corrected their site after I emailed to the webmaster on friday with the bug.
As a buzy research student currently writing his thesis I have no time to sit about and play with LEGO all day.
Oh wait no. Thats what I do all day every day while avoiding work.
Anyway after making a internet controllable camera and an internet controllable robot, I have run out of inspiration.
The research group lego has two motors and I want to make something that people can control over the internet. Any suggestions?
If they can get linux running on an old IBM platform like PS/2 then I will get my old computer out the attic.
PS/2 = Old IBM PC standard (we still have the keyboard and mouse connectors as a legacy)
PS2 = Sony games machine