The advantage of the ARM business model is that you don't have to. Anybody can get a license from ARM to put a core in an ASIC. This means that is very easy to build an integrated system on a chip around a CPU and any kind of peripherals you want.
This is Intel's attempt to capture some of that market. But because they don't want to license their core, their trying to tie it to an FPGA. I have doubts whether this will be attractive. FPGAs are slow, use more power, and are more expensive compared to ASICs. For high-volume products they can't compete on price, and for high-performance products they can't compete on speed.
The '93 era Pentium they're talking about only has 3 million transistors, and only a fraction are needed to handle the x86 instruction set. Current transistor count goes into the billions, so as far as real estate goes, you can put 1000 Pentium class cores on a single die, despite the x86 translations.
Of course, the whole concept of a 1000 cores running on a single die is only going to serve a small niche of applications.
We way we do it now is a single filesystem layer which is, at all times, in a single coherent state. With today's shared memory systems, and cache coherency guaranteed by the hardware, that's reasonable easy to accomplish.
The current filesystem concept just doesn't map onto 1000 non-coherent cores.
Examples? It's just a different model, it's doesn't prevent you solving any problem.
A typical consumer desktop machine, running typical programs for instance. In order to use these cores effectively, all these programs need to rewritten. Imagine your word processor reformatting a 500 page document on 1000 cores. It's just not going to work very well.
How about the operating system ? 1000 different cores all trying to access a file system on a single physical drive. How are you going to run that efficiently ?
There's a third option: combine the best of both worlds. Use powerful, superscalar cores with shared memory, as powerful as you can reasonably make them, and then run clusters of those in parallel.
You just don't program a massively parallel architecture in the same way as a shared memory one.
Well, there's your problem. Many real world applications can only be programmed that way.
And the fact that multiple simple cores are currently on the market doesn't mean they're not failures. The ClearSpeed 192-core CSX700 is on the market, but nobody is buying it. In my book that's a failure.
The thing is, if you want to put more cores on a die, you need either a bigger die or smaller cores
Nobody wants to put more cores on a die, but they're forced to do so because they reach the limits of a single core. I'd rather have as few cores as possible, but have each one be really powerful. Once multiple cores are required, I'd want them to stretch the coherent shared memory concept as far as it will go. When that concept doesn't scale anymore, use something like NUMA.
Small, message passing cores have been tried multiple times, and they've always failed. The problem is that the requirement of distributed state coherency doesn't go away. The burden only gets shifted from the hardware to the software, where it is just as hard to accomplish, but much slower. In addition, if you try to tackle the coherency problem in software, you don't get to benefit from hardware improvements.
Err, did you just claim cache is as fast as a register access?
There's no reason why it shouldn't be. Don't forget that register access comes with the overhead of load/store plus the fact that you may have to save the register when calling a function, and during interrupts/context switches. Direct memory access doesn't have all that overhead, and if you throw enough control logic around it, a small cache can be just as fast.
Memory also offers the possibility of storing other things than 32/64 bit integers, such as character strings and local structs, so any optimization done to aggressively cache local stack access will also benefit that kind of code. Try doing an efficient strcpy() on an ARM for instance.
The only reason x86 is still around (i.e. successful) is because it's pretty much backwards compatible since the 8086- which is over THIRTY YEARS OLD.
That's a clear testament to scalability when you consider the speed improvement in the last 30 years using basically the same ISA.
you might be interested to find out that you can have a fifteen byte instruction
So ? It's not the maximum instruction length that counts, but the average. In typical programs that's closer to three. Frequently used opcodes like push/pop only take a single byte. Compare to a DEC Alpha architecture, where nearly every single instruction uses 15 bits just to tell which registers are used, no matter whether a function needs that many registers.
If Intel would just abandon x86, they could reduce their cores by something like 50%!
Even if that's true (I doubt it), who cares ? The problem is not intel has too many transistors for a given area. The problem is just the opposite. They have the capability to put more transistors in a core that they know what to do with. Also, typically half the chip is for the cache memories, and the compact instruction set helps to use that cache memory more effectively.
one cannot simply rely on a shared memory architecture to scale vertically indefinitely
Sure you can. Shared memory architectures can do everything explicit channel communication architectures can do, plus you have the benefit that the communication details are hidden from the programmer, allowing improvements to the implementation without having to rewrite your software. Sure, the hardware is more complex, but transistors are dirt cheap, so I'd rather put the complexity in the hardware.
There's also no reason to throw away an ISA that has proven to be extremely scalable and very successful, just because it's ancient or it looks ugly.
The advantage of the x86 instruction set is that it's very compact. It comes at a price of increased decoding complexity, but that problem has already been solved.
The low number of registers is not a problem. In fact, it may even be an advantage to scalability. A register is nothing more than a programmer-controlled mini cache in front of the memory. I'd rather have few registers, and go directly to memory. The hardware can then scale to include bigger and faster caches, so that memory access is just as fast a register access, without the software having to deal with register allocation and save/restore.
Dialogues between people have limited vertical content. Once you show a person head to toe, there's nothing more to add. Horizontal space gives the director more freedom to let the characters move around during their dialogue.
The traffic jam is 9 days old. That doesn't mean the cars are stuck in there for 9 days. It could be that each car travels through the entire traffic jam in a few hours, but as soon as it's through, another car gets in line at the end.
You can make it from radioactive materials that emit alpha radiation. That's how it was made in the earth too. Production volume will be very low, though.
Instead of worrying about finding intelligence, let's just look for any kind of anomaly. Even if you don't find any life forms, you may still find natural things that turn out to be interesting (like pulsars for instance).
I didn't say it wasn't difficult to do. It's like climbing Mt. Everest without oxygen, or crossing Antarctica by foot. Excellent jobs, but not terribly useful in the end.
Even if you find the right mix of materials for the heat shield, you'll still need to get the angle just right. Too steep, and the g-forces will kill you, the shield will get extremely hot, and it will be subjected to huge pressures. Too shallow, and the heat shield will be subjected to heat for much longer, so it has time to conduct through.
Jumping out with a regular parachute on your back requires an accurate landing. It's not so much fun in the middle of the Atlantic with nobody near your location.
Considering that the energy requirements for getting to orbit are actually a little bit easier than a flight from London to Sydney
With a crucial difference that a flight from Londen to Sydney takes half a day, and a launch to LEO only a few minutes. This adds a bit of complexity to the systems. Also, the engineering margins on a rocket are going to be much smaller. Some materials are designed to be operated close to melting points, or breaking stresses. This is necessary, because something over-engineered will be too heavy to lift off. Running so close to the envelope requires much more careful design, testing, and manufacturing, which all adds to the cost.
Would you be able to tell if your own consciousness was faked ?
Eventually, someone is going to figure out how it works
Even if somebody does, the answer may still require such a shift in people's perception, that they won't accept the answer. What if it turns out to be all fake, could you accept that ?
Sure, I agree that research of all kinds of low-gravity experiments would be useful to bring back to earth. However, that's something that can be done on a small capsule, like the one they are testing right now, possibly using an unmanned configuration. So, far what they are doing right now, the SpaceX design seems pretty good, even though it looks like a step back.
As far as large scale manufacturing in low-gravity environment, I think that'll have to wait until somebody invents a radically different way to get to and from orbit. Even with SpaceX's affordable rates, it's still very expensive.
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The advantage of the ARM business model is that you don't have to. Anybody can get a license from ARM to put a core in an ASIC. This means that is very easy to build an integrated system on a chip around a CPU and any kind of peripherals you want.
This is Intel's attempt to capture some of that market. But because they don't want to license their core, their trying to tie it to an FPGA. I have doubts whether this will be attractive. FPGAs are slow, use more power, and are more expensive compared to ASICs. For high-volume products they can't compete on price, and for high-performance products they can't compete on speed.
This is not a soft core CPU. You get a package with 2 dies inside: a regular Intel Atom CPU core, and a separate FPGA.
With 'direct memory access' I was referring to a CISC instruction set that could directly access memory as one or more of its operands. Like this:
add 0x8001, 0x8002
Which is just a single instruction.
The '93 era Pentium they're talking about only has 3 million transistors, and only a fraction are needed to handle the x86 instruction set. Current transistor count goes into the billions, so as far as real estate goes, you can put 1000 Pentium class cores on a single die, despite the x86 translations.
Of course, the whole concept of a 1000 cores running on a single die is only going to serve a small niche of applications.
We way we do it now is a single filesystem layer which is, at all times, in a single coherent state. With today's shared memory systems, and cache coherency guaranteed by the hardware, that's reasonable easy to accomplish.
The current filesystem concept just doesn't map onto 1000 non-coherent cores.
A typical consumer desktop machine, running typical programs for instance. In order to use these cores effectively, all these programs need to rewritten. Imagine your word processor reformatting a 500 page document on 1000 cores. It's just not going to work very well.
How about the operating system ? 1000 different cores all trying to access a file system on a single physical drive. How are you going to run that efficiently ?
There's a third option: combine the best of both worlds. Use powerful, superscalar cores with shared memory, as powerful as you can reasonably make them, and then run clusters of those in parallel.
Well, there's your problem. Many real world applications can only be programmed that way.
And the fact that multiple simple cores are currently on the market doesn't mean they're not failures. The ClearSpeed 192-core CSX700 is on the market, but nobody is buying it. In my book that's a failure.
Nobody wants to put more cores on a die, but they're forced to do so because they reach the limits of a single core. I'd rather have as few cores as possible, but have each one be really powerful. Once multiple cores are required, I'd want them to stretch the coherent shared memory concept as far as it will go. When that concept doesn't scale anymore, use something like NUMA.
Small, message passing cores have been tried multiple times, and they've always failed. The problem is that the requirement of distributed state coherency doesn't go away. The burden only gets shifted from the hardware to the software, where it is just as hard to accomplish, but much slower. In addition, if you try to tackle the coherency problem in software, you don't get to benefit from hardware improvements.
There's no reason why it shouldn't be. Don't forget that register access comes with the overhead of load/store plus the fact that you may have to save the register when calling a function, and during interrupts/context switches. Direct memory access doesn't have all that overhead, and if you throw enough control logic around it, a small cache can be just as fast.
Memory also offers the possibility of storing other things than 32/64 bit integers, such as character strings and local structs, so any optimization done to aggressively cache local stack access will also benefit that kind of code. Try doing an efficient strcpy() on an ARM for instance.
That's a clear testament to scalability when you consider the speed improvement in the last 30 years using basically the same ISA.
So ? It's not the maximum instruction length that counts, but the average. In typical programs that's closer to three. Frequently used opcodes like push/pop only take a single byte. Compare to a DEC Alpha architecture, where nearly every single instruction uses 15 bits just to tell which registers are used, no matter whether a function needs that many registers.
Even if that's true (I doubt it), who cares ? The problem is not intel has too many transistors for a given area. The problem is just the opposite. They have the capability to put more transistors in a core that they know what to do with. Also, typically half the chip is for the cache memories, and the compact instruction set helps to use that cache memory more effectively.
Sure you can. Shared memory architectures can do everything explicit channel communication architectures can do, plus you have the benefit that the communication details are hidden from the programmer, allowing improvements to the implementation without having to rewrite your software. Sure, the hardware is more complex, but transistors are dirt cheap, so I'd rather put the complexity in the hardware.
There's also no reason to throw away an ISA that has proven to be extremely scalable and very successful, just because it's ancient or it looks ugly.
The advantage of the x86 instruction set is that it's very compact. It comes at a price of increased decoding complexity, but that problem has already been solved.
The low number of registers is not a problem. In fact, it may even be an advantage to scalability. A register is nothing more than a programmer-controlled mini cache in front of the memory. I'd rather have few registers, and go directly to memory. The hardware can then scale to include bigger and faster caches, so that memory access is just as fast a register access, without the software having to deal with register allocation and save/restore.
Dialogues between people have limited vertical content. Once you show a person head to toe, there's nothing more to add. Horizontal space gives the director more freedom to let the characters move around during their dialogue.
4.Once found, use number to produce compact William Shakespeare quote generator.
Why would you assume the number is any shorter than the original works of Shakespeare ?
The traffic jam is 9 days old. That doesn't mean the cars are stuck in there for 9 days. It could be that each car travels through the entire traffic jam in a few hours, but as soon as it's through, another car gets in line at the end.
Your basic blimp is also slow, can't carry much weight, and can't deal with storms very well.
You can make it from radioactive materials that emit alpha radiation. That's how it was made in the earth too. Production volume will be very low, though.
Instead of worrying about finding intelligence, let's just look for any kind of anomaly. Even if you don't find any life forms, you may still find natural things that turn out to be interesting (like pulsars for instance).
I was talking about entry vehicles with a live astronaut whom you don't want to turn into toast or jelly.
I didn't say it wasn't difficult to do. It's like climbing Mt. Everest without oxygen, or crossing Antarctica by foot. Excellent jobs, but not terribly useful in the end.
Even if you find the right mix of materials for the heat shield, you'll still need to get the angle just right. Too steep, and the g-forces will kill you, the shield will get extremely hot, and it will be subjected to huge pressures. Too shallow, and the heat shield will be subjected to heat for much longer, so it has time to conduct through.
Jumping out with a regular parachute on your back requires an accurate landing. It's not so much fun in the middle of the Atlantic with nobody near your location.
But not much less dangerous
Orbital is much more dangerous. Re-entry at hypersonic speeds is not an easy problem to solve.
Even though it's a nice achievement, a suborbital rocket is basically a glorified carnival ride, a couple of magnitudes easier than fully orbital.
Considering that the energy requirements for getting to orbit are actually a little bit easier than a flight from London to Sydney
With a crucial difference that a flight from Londen to Sydney takes half a day, and a launch to LEO only a few minutes. This adds a bit of complexity to the systems. Also, the engineering margins on a rocket are going to be much smaller. Some materials are designed to be operated close to melting points, or breaking stresses. This is necessary, because something over-engineered will be too heavy to lift off. Running so close to the envelope requires much more careful design, testing, and manufacturing, which all adds to the cost.
Consciousness could be 'faked'.
Would you be able to tell if your own consciousness was faked ?
Eventually, someone is going to figure out how it works
Even if somebody does, the answer may still require such a shift in people's perception, that they won't accept the answer. What if it turns out to be all fake, could you accept that ?
Sure, I agree that research of all kinds of low-gravity experiments would be useful to bring back to earth. However, that's something that can be done on a small capsule, like the one they are testing right now, possibly using an unmanned configuration. So, far what they are doing right now, the SpaceX design seems pretty good, even though it looks like a step back.
As far as large scale manufacturing in low-gravity environment, I think that'll have to wait until somebody invents a radically different way to get to and from orbit. Even with SpaceX's affordable rates, it's still very expensive.