Have you looked at SDC-based time constraints? Altera has already moved there with TimeQuest. They bring the FPGA world up to the time-constraint-quality of ASICs. Xilinx I'm sure will move soon as well.
after a week training course write in it with professional quality
This is what suits actually believe.
This is what I believe, and I'm a good engineer who codes professionally in VHDL, but has never coded in Verilog (although I have read and understood Verilog files as required).
Centuries ago, and are distinct now. You know, like every other "ethnically distict" group came from African's at some point, and became distinct through cultural and physical isolation.
In case you haven't been following it, Brent Spiner is telling a short story through his Twitter account, one sentence at a time. (Or so says my wife; I don't use those newfangled interwebs 2.0 things.)
Having now read through the entirety of the comments on this story, the trend I see is that: A) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine, while B) students who learned with Verilog then went on to a career with VHDL, while rarer, think VHDL is a harder language, and C) students who were forced to take VHDL when it wasn't in their career plan hated it, because it was so different than a programming language.
Based on that review, I'd say teach your students VHDL. The students that learn it and do well in your course will have the easiest time in the industry, and those that hate it probably won't become good HDL designers regardless.
I work for a company that might be the VHDL-user you mention. I think students who learned VHDL produce code closer to production quality sooner, but it's not very different as you state. Verilog students just need more time to get used to the increased structure requirements of VHDL. I don't ask questions that require either during interviews - the underlying logic of system design is far more important.
If Verilog is moving towards stricter types as I've heard it to be, this difference will close up soon.
(Note that I learned neither in college but was hired based on that underlying logic basis. My HDL education started with a course offered by my employer. It now represents some 80% of my daily work.)
No one is doing schematic design for FPGAs any more. If you want to teach schematic design, get a schematic capture and layout package and teach PCB design. There are plenty of things to learn at the board-design level, too, and you can teach some of your circuit theory that way if you wish.
Ford is in pretty good shape, not because of their truck divisions but because they didn't abandon cars entirely and join their competition in a round of "Americans! Ugrg Ugrg big trucks low mileage screw quality!". While I have only briefly driven them, I understand that the Ford Focus is a rather popular, higher-quality vehicle for its price range. Cars like that saved them more than anything else.
The biggest problem with Xilinx' compilation software at the moment is their timing analysis. The industry is moving towards system models for timing analysis, based around Synopsys Design Constraints. Their use in ASICs is already pretty common, but for FPGA design their use is pretty new.
Altera's TimeQuest analyzer in their Quartus II software is SDC-based, so learning that gets you the latest and greatest in terms of analysis capabilities. Xilinx still uses classical, chip-centric timing analysis software. I would expect an SDC-based model from them in the near future, but if you learn with what they currently offer, you'll need to learn again.
That said, you'll have success with either company at this point. The Altera Max+Plus II software I was forced to use in college was some of the buggiest, least-intuitive, poorest quality software I've ever seen. But the latest versions of Quartus II are good enough to be better than most third-party tools for synthesis, and perfectly functional for place and route and analysis.
Verilog is more popular in the ASIC design industry, for certain. But I work at a large test instrument manufacturer whose products are based heavily on FGPA design, and we are exclusively a VHDL shop.
It is my understanding that Verilog is moving towards stricter type definitions, so that it can get some of the benefits that entails. If you, the submitter, are looking to learn/teach a language least likely to change in the near term, go with VHDL.
That said, a good engineer should be able to sit down with the unfamiliar language and read it, and after a week training course write in it with professional quality. So whichever you teach, your good students will do fine in their careers.
Of course you're not. We wouldn't allow another state into the union that's bigger than Texas (we already made that mistake once). Canada is more like a protectorate, like Puerto Rico, in that you don't get to vote for anything or pay income taxes but we make all your decisions.
Although something tells me that Nigeria isn't neccessarily most prominent market for apple, since price of an iphone is equal to one years salary for an average nigerian.
That's just because the average Nigerian's money is caught up in an off-shore bank account, and we aren't doing our part to help them access the funds despite the generous offer of 10% commission.
Actually, if you watch Better Off Ted, I think the character Ted is supposed to show someone completely lacking of any personality disorders. Part of the show's charm is how totally unrealistic he is.
I suspect a psychiatrist could find something wrong with his unusually cheerful demeanor and prescribe something right away.
simplify the laws, put normal 'thinking' people in charge as judges and we could NOT do a worse job than is being done now. not joking about it either, the system is just too complex and needs to be totally broken down and redone.
lawyers are slime and the fact that you 'need' them indicates a bigger social problem.
"Normal, 'thinking' people" can arrive at drastically different conclusions. See Conservative v. Liberal v. Libertarian. So, if you want the law to be consistent, what your saying is that we should scrap all the existing precendences, but start over reestablishing them, which will eventually require lawyers again.
Or, do you intend to abolish precedence, and let each judge conclude for each case how to interpret and apply the law? Because I see the world where judges can arbitrarily apply law with no regard for established precedence to be far, far worse than the world we have now.
I find it funny that virtually every reply on slashdot denigrates tritter. While I don't use it, I also don't use IM or text messages or anything newer than email & web. But I still see that it has value for people who find daily interconnections with other people refreshing.
That said, Brent Spiner is on tritter. Do you know how he's using it? He's publishing a work of narrative fiction. Once sentence at a time. As a concept, it's actually quite interesting.
Slashdot Mirror
Have you looked at SDC-based time constraints? Altera has already moved there with TimeQuest. They bring the FPGA world up to the time-constraint-quality of ASICs. Xilinx I'm sure will move soon as well.
This is what suits actually believe.
This is what I believe, and I'm a good engineer who codes professionally in VHDL, but has never coded in Verilog (although I have read and understood Verilog files as required).
Centuries ago, and are distinct now. You know, like every other "ethnically distict" group came from African's at some point, and became distinct through cultural and physical isolation.
But none of those people are Japanese. They are all gaijin, not nihonjin. Passport does not matter. It's an important difference to them.
In case you haven't been following it, Brent Spiner is telling a short story through his Twitter account, one sentence at a time. (Or so says my wife; I don't use those newfangled interwebs 2.0 things.)
Having now read through the entirety of the comments on this story, the trend I see is that:
A) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine, while
B) students who learned with Verilog then went on to a career with VHDL, while rarer, think VHDL is a harder language, and
C) students who were forced to take VHDL when it wasn't in their career plan hated it, because it was so different than a programming language.
Based on that review, I'd say teach your students VHDL. The students that learn it and do well in your course will have the easiest time in the industry, and those that hate it probably won't become good HDL designers regardless.
I work for a company that might be the VHDL-user you mention. I think students who learned VHDL produce code closer to production quality sooner, but it's not very different as you state. Verilog students just need more time to get used to the increased structure requirements of VHDL. I don't ask questions that require either during interviews - the underlying logic of system design is far more important.
If Verilog is moving towards stricter types as I've heard it to be, this difference will close up soon.
(Note that I learned neither in college but was hired based on that underlying logic basis. My HDL education started with a course offered by my employer. It now represents some 80% of my daily work.)
No one is doing schematic design for FPGAs any more. If you want to teach schematic design, get a schematic capture and layout package and teach PCB design. There are plenty of things to learn at the board-design level, too, and you can teach some of your circuit theory that way if you wish.
Ford is in pretty good shape, not because of their truck divisions but because they didn't abandon cars entirely and join their competition in a round of "Americans! Ugrg Ugrg big trucks low mileage screw quality!". While I have only briefly driven them, I understand that the Ford Focus is a rather popular, higher-quality vehicle for its price range. Cars like that saved them more than anything else.
?? What you state makes no sense. I use VI as my text editor and EMACS as my operating system.
The biggest problem with Xilinx' compilation software at the moment is their timing analysis. The industry is moving towards system models for timing analysis, based around Synopsys Design Constraints. Their use in ASICs is already pretty common, but for FPGA design their use is pretty new.
Altera's TimeQuest analyzer in their Quartus II software is SDC-based, so learning that gets you the latest and greatest in terms of analysis capabilities. Xilinx still uses classical, chip-centric timing analysis software. I would expect an SDC-based model from them in the near future, but if you learn with what they currently offer, you'll need to learn again.
That said, you'll have success with either company at this point. The Altera Max+Plus II software I was forced to use in college was some of the buggiest, least-intuitive, poorest quality software I've ever seen. But the latest versions of Quartus II are good enough to be better than most third-party tools for synthesis, and perfectly functional for place and route and analysis.
Verilog is more popular in the ASIC design industry, for certain. But I work at a large test instrument manufacturer whose products are based heavily on FGPA design, and we are exclusively a VHDL shop.
It is my understanding that Verilog is moving towards stricter type definitions, so that it can get some of the benefits that entails. If you, the submitter, are looking to learn/teach a language least likely to change in the near term, go with VHDL.
That said, a good engineer should be able to sit down with the unfamiliar language and read it, and after a week training course write in it with professional quality. So whichever you teach, your good students will do fine in their careers.
Japan started fingerprinting visitors in late 2007 or early 2008, just after I visited. It's a shame, really; I'd like to go back.
The Japanese?
Of course you're not. We wouldn't allow another state into the union that's bigger than Texas (we already made that mistake once). Canada is more like a protectorate, like Puerto Rico, in that you don't get to vote for anything or pay income taxes but we make all your decisions.
(I jest.)
Posting to fix a bad moderation. Sorry. WTB confirmation button.
Although something tells me that Nigeria isn't neccessarily most prominent market for apple, since price of an iphone is equal to one years salary for an average nigerian.
That's just because the average Nigerian's money is caught up in an off-shore bank account, and we aren't doing our part to help them access the funds despite the generous offer of 10% commission.
All I see is a tan box with a crossed out snake in the corner.
Actually, if you watch Better Off Ted, I think the character Ted is supposed to show someone completely lacking of any personality disorders. Part of the show's charm is how totally unrealistic he is.
I suspect a psychiatrist could find something wrong with his unusually cheerful demeanor and prescribe something right away.
How much of that air do you exhale?
http://www.washingtonpost.com/wp-dyn/content/article/2006/08/30/AR2006083001418.html
simplify the laws, put normal 'thinking' people in charge as judges and we could NOT do a worse job than is being done now. not joking about it either, the system is just too complex and needs to be totally broken down and redone.
lawyers are slime and the fact that you 'need' them indicates a bigger social problem.
"Normal, 'thinking' people" can arrive at drastically different conclusions. See Conservative v. Liberal v. Libertarian. So, if you want the law to be consistent, what your saying is that we should scrap all the existing precendences, but start over reestablishing them, which will eventually require lawyers again.
Or, do you intend to abolish precedence, and let each judge conclude for each case how to interpret and apply the law? Because I see the world where judges can arbitrarily apply law with no regard for established precedence to be far, far worse than the world we have now.
Blurb is free; copying the title into a google bar and clicking on the first free result is also free.
I find it funny that virtually every reply on slashdot denigrates tritter. While I don't use it, I also don't use IM or text messages or anything newer than email & web. But I still see that it has value for people who find daily interconnections with other people refreshing.
That said, Brent Spiner is on tritter. Do you know how he's using it? He's publishing a work of narrative fiction. Once sentence at a time. As a concept, it's actually quite interesting.
Use rice paper, then you can eat any extra printouts.
Soy Ink on Rice Paper? Eat your words!
Plus I use a wasabi highlighter. Then when I'm done I can use my waste paper to wrap a fresh piece of fish. Voila! Instant sushi!