The ratings given to reviewed books are useless as it is now. Most books are given an 8 or 9, and there doesn't seem to be any system for how to rate the books. For example, the last X books that I looked up under book reviews were given: 7/10, 9, 9/10, 6/10, 8, 8/10, 8/10, 9, 9, 9/10, 9, 8, 8/10, 7/10, 10. The reviewers don't even know if there should be a "/10" in the rating or not. I've also seen ratings on a 1 to 5 scale.
It would be better, if different parts and aspects of the books were given separate ratings, and then a total rating was calculated from the parts. Please also look into how other publications rate books. I'm sure there's a lot to be learned.
For those who actually want to try out this, go to http://ilovemountains.org/memorial_tutorial/. It describes which layers to turn on in Google Earth to be able to see the Appalachian mountains removal.
Comparison of Refractive Index between Transparent Ceramics and Conventional Optical Glass The refractive index of the transparent ceramics is 2.08 (lambda = 587 nm). It is quite high compared with that of conventional optical glasses (between 1.5 to 1.8). Furthermore, as there is no birefringence in the ceramics, there is a potential for downsizing and advancement of optical devices with optical elements, such as lenses.
The press release (http://www.jensofsweden.com/media/MP-130/Pressmed delande-JOS-MP-130-040504-sv.pdf) which is in Swedish, claims that the display is OLED.
"Spegelspelarens 96 x 40 mm skärm bygger på ny organisk LED-teknik (Organic Light Emitting Display)." which translates to "The 96 x 40 mm screen of the mirror player is built on an organic LED technology..."
Asynchronous CPUs have existed for a while. They don't seem to have
become very popular, though. Apparently, they don't give the
power/speed advantage that you would expect at first glance.
A quick search with Google gave this:
helge: >>That's the reason why modern digital chips are >>powered by ever decreasing voltage.
bperkins: >I doubt many CMOS transistors are anywhere near >their breakdown regime. Reduced power >consumption and heat disapation is the primary >reason for reducing volatge.
MOS transistors are often operating near their breakdown regime because doing otherwise would be a waste of speed and power. The reason could be found in the formula for the drain current of the transistor in the saturation region:
The drain current is proportional to kp*(W/L)*(Vgs-Vt)^2 where L is the length of the channel (in the direction of the current), W is the width of the channel, Vgs is the gate-to-source voltage and Vt is the threshold voltage of the device.
The drain current is used to charge capacitors; the capacitive load of both wires and gates of other transistors. Therefore, speed is proportional to this current. The largest Vgs that can be obtained is the supply voltage. Therefore, larger supply voltage means higher speed. It also means higher power dissipation, because those capacitors are charged to a higher voltage. But the speed increase with the square of the supply voltage and the power only increase linearly, so you still gain by using higher supply voltage.
The drain current can also be increased by lowering L. Speed will increase in reverse proportion. But at the same time, the breakdown voltage between drain and source will be lower. It doesn't mean that the device is damaged, but it's still not something you wish. This breakdown voltage is usually rated a bit above the supply voltage, say 4.5 volts for a 3.3 volt supply.
The drain current and thus speed can also be increased by making the gate oxide thinner. The parameter kp in the above formula is reverse proportional to the thickness of the gate oxide. The circuit designer cannot do anything about this, but the process designer can. Again, the breakdown voltage will be lower, and the acceptable voltage over the gate oxide is not much larger than the supply voltage. A high quality gate oxide would help, because it would tolerate a higher electrical field. Current through the gate will usually damage the device, therefore it's important to protect them from, e.g., ESD pulses.
As for the chip density: The gates of ordinary MOS transistors are made with the same photolithographic process as the metal wires, so the evolution in feature size applies to both. For memory chips, you are probably right in that most of the area is populated by transistors. But for analog chips, wiring dominates. Also, a transistor has three terminals, all which must be connected. With a feature size of 0.5 um, the contacts will in reality be more than 1 um wide, even though the gate is only 0.5 um long. The method used by Bell Labs in their report doesn not apply to the contacts, only to the gate.
There are different kinds of smallness for transistors. One is the size of the active part; for MOS transistors it's the channel under the gate, which is lateral (horizontal). For bipolar transistors, it's the base region between collector and emitter, where the current flows vertically. Thus bipolar transistors are (usually) called vertical.
Smallness in the active part allows higher speed (usually referred to with the parameters ft or fmax) but it also means that the transistor breaks down at a smaller voltage. That's the reason why modern digital chips are powered by ever decreasing voltage.
But the active part of the transistor is small compared to the rest of it. It must have contacts to lead the current to and from the transistor. And then the complete transistors only occupy a small area of the chips, the most of it is used for wiring.
So just because some vertical dimension of a transistor has shrunk to 50 nm doesn't mean that you can fit very many of them on a chip. That depends more on how thin wires you can make, and how many layers. No wonder that modern chips can have as many as five layers of wiring, something that was very difficult to do ten years ago.
The scientists at Bell Labs has shrunk the active region of what appears to be an MOS transistor. It will be fast, but the number of transistors on a chip will not increase as a result.
I found an article about the transistor at http://www.bell-labs.com/news/1999/november/15/1 .html
Slashdot Mirror
The ratings given to reviewed books are useless as it is now. Most books are given an 8 or 9, and there doesn't seem to be any system for how to rate the books. For example, the last X books that I looked up under book reviews were given: 7/10, 9, 9/10, 6/10, 8, 8/10, 8/10, 9, 9, 9/10, 9, 8, 8/10, 7/10, 10. The reviewers don't even know if there should be a "/10" in the rating or not. I've also seen ratings on a 1 to 5 scale.
It would be better, if different parts and aspects of the books were given separate ratings, and then a total rating was calculated from the parts. Please also look into how other publications rate books. I'm sure there's a lot to be learned.
For those who actually want to try out this, go to http://ilovemountains.org/memorial_tutorial/. It describes which layers to turn on in Google Earth to be able to see the Appalachian mountains removal.
It seems that the dupe of this article http://slashdot.org/comments.pl?sid=129334 "Google Cranks Up Index" is removed! Is this the first time it happens on Slashdot?
The lens is made by MuRata and is called Lumicera. Info can be found at http://www.murata.com/opt/lumicera.html
Comparison of Refractive Index between Transparent Ceramics and Conventional Optical Glass
The refractive index of the transparent ceramics is 2.08 (lambda = 587 nm). It is quite high compared with that of conventional optical glasses (between 1.5 to 1.8). Furthermore, as there is no birefringence in the ceramics, there is a potential for downsizing and advancement of optical devices with optical elements, such as lenses.
The press release (http://www.jensofsweden.com/media/MP-130/Pressmed delande-JOS-MP-130-040504-sv.pdf) which is in Swedish, claims that the display is OLED.
..."
"Spegelspelarens 96 x 40 mm skärm bygger på ny organisk LED-teknik (Organic Light Emitting Display)." which translates to
"The 96 x 40 mm screen of the mirror player is built on an organic LED technology
Asynchronous ARM core nears commercial debut (1998)
ARM researches asynchronous CPU design (feb 1995)
AMULET3: A High-Performance Self-Timed ARM Microprocessor (1998)
helge:
>>That's the reason why modern digital chips are
>>powered by ever decreasing voltage.
bperkins:
>I doubt many CMOS transistors are anywhere near >their breakdown regime. Reduced power
>consumption and heat disapation is the primary >reason for reducing volatge.
MOS transistors are often operating near their breakdown regime because doing otherwise would be a waste of speed and power. The reason could be found in the formula for the drain current of the transistor in the saturation region:
The drain current is proportional to kp*(W/L)*(Vgs-Vt)^2
where L is the length of the channel (in the direction of the current), W is the width of the channel, Vgs is the gate-to-source voltage and Vt is the threshold voltage of the device.
The drain current is used to charge capacitors; the capacitive load of both wires and gates of other transistors. Therefore, speed is proportional to this current. The largest Vgs that can be obtained is the supply voltage. Therefore, larger supply voltage means higher speed. It also means higher power dissipation, because those capacitors are charged to a higher voltage. But the speed increase with the square of the supply voltage and the power only increase linearly, so you still gain by using higher supply voltage.
The drain current can also be increased by lowering L. Speed will increase in reverse proportion. But at the same time, the breakdown voltage between drain and source will be lower. It doesn't mean that the device is damaged, but it's still not something you wish. This breakdown voltage is usually rated a bit above the supply voltage, say 4.5 volts for a 3.3 volt supply.
The drain current and thus speed can also be increased by making the gate oxide thinner. The parameter kp in the above formula is reverse proportional to the thickness of the gate oxide. The circuit designer cannot do anything about this, but the process designer can. Again, the breakdown voltage will be lower, and the acceptable voltage over the gate oxide is not much larger than the supply voltage. A high quality gate oxide would help, because it would tolerate a higher electrical field. Current through the gate will usually damage the device, therefore it's important to protect them from, e.g., ESD pulses.
As for the chip density: The gates of ordinary MOS transistors are made with the same photolithographic process as the metal wires, so the evolution in feature size applies to both. For memory chips, you are probably right in that most of the area is populated by transistors. But for analog chips, wiring dominates. Also, a transistor has three terminals, all which must be connected. With a feature size of 0.5 um, the contacts will in reality be more than 1 um wide, even though the gate is only 0.5 um long. The method used by Bell Labs in their report doesn not apply to the contacts, only to the gate.
There are different kinds of smallness for transistors. One is the size of the active part; for MOS transistors it's the channel under the gate, which is lateral (horizontal). For bipolar transistors, it's the base region between collector and emitter, where the current flows vertically. Thus bipolar transistors are (usually) called vertical.
1 .html
Smallness in the active part allows higher speed (usually referred to with the parameters ft or fmax) but it also means that the transistor breaks down at a smaller voltage. That's the reason why modern digital chips are powered by ever decreasing voltage.
But the active part of the transistor is small compared to the rest of it. It must have contacts to lead the current to and from the transistor. And then the complete transistors only occupy a small area of the chips, the most of it is used for wiring.
So just because some vertical dimension of a transistor has shrunk to 50 nm doesn't mean that you can fit very many of them on a chip. That depends more on how thin wires you can make, and how many layers. No wonder that modern chips can have as many as five layers of wiring, something that was very difficult to do ten years ago.
The scientists at Bell Labs has shrunk the active
region of what appears to be an MOS transistor. It will be fast, but the number of transistors on a chip will not increase as a result.
I found an article about the transistor at
http://www.bell-labs.com/news/1999/november/15/