At first glance, I thought the headline stated "Attempts to Court Linux Users Remain Pointless" and was confused... I wasn't sure where the news was in that statement.
Well, it was formatted nicely when I typed it out, I should have used the preview button, but being in a hurry to get my first post on slashdot done, I just hit submit, not noticing the posting type, so I apologize for the poor formatting.
There are two quotes in my post, one from the first article and the other from a comment on the second article. I should have stated it was a users comment, but figured it would be fine as thats exactly what this forum is. For anyone who's interested enough to read these offtopic posts, now they'll know and my post will be formatted better next time;)
I just wanted to point that out, I think some posters are thinking about it incorrectly:
"The 500 GHz mark was the goal when Feng and UI colleagues received a $2.1 million, five-year grant for the project from the Defense Advanced Research Projects Agency in October. In contrast, the transistors inside the central chip of a powerful personal computer run at around 50 or 100 GHz, Feng said. The fastest that such a chip runs as a package is currently around 3 GHz."
http://www.news-gazette.com/news/local/2003/01/24/ fastest_transistor_made_at_ui/
In addition, University of Illinois broke 600 Ghz last year.
http://www.physorg.com/news3662.html
"The speeds quoted in this article are maximum rated *switching* speeds of a single transistor. Synchronous logic designs of the type found in microprocessors involve synchronous cells (known as flip-flops) and asynchronous gates providing boolean functions on the signals passing between flip-flops. The maximum rated frequency of any design is limited by the slowest path between flip-flops and this is what the clock signal will be set at.
As the paths between the clocked flip-flops are typically anywhere between 2 and 10 logic cells deep and with each one comprising 10's of transistors (usually in complementary configuration to aid switching speed), the overall figure for an ASIC design such as a uProcessor would be at least 2-4 times slower than the maximum transistor switching speed (it's not quite cumulative, because as one transistor starts switching, the voltage at the at the `gate' of the next one has already started changing causing it to start conducting, and so on). I also have a suspicion that there would be other real-world constraints such as cross-talk (noise between transistors) and thermal problems. I'd hazard a guess that a production-quality chip would be somewhere in the region of a tenth the speeds quoted here!
However, these new materials and structures still make for an impressive speed gain over traditional Silicon CMOS designs." (The speeds quoted in this article are maximum rated *switching* speeds of a single transistor. Synchronous logic designs of the type found in microprocessors involve synchronous cells (known as flip-flops) and asynchronous gates providing boolean functions on the signals passing between flip-flops. The maximum rated frequency of any design is limited by the slowest path between flip-flops and this is what the clock signal will be set at.
As the paths between the clocked flip-flops are typically anywhere between 2 and 10 logic cells deep and with each one comprising 10's of transistors (usually in complementary configuration to aid switching speed), the overall figure for an ASIC design such as a uProcessor would be at least 2-4 times slower than the maximum transistor switching speed (it's not quite cumulative, because as one transistor starts switching, the voltage at the at the `gate' of the next one has already started changing causing it to start conducting, and so on). I also have a suspicion that there would be other real-world constraints such as cross-talk (noise between transistors) and thermal problems. I'd hazard a guess that a production-quality chip would be somewhere in the region of a tenth the speeds quoted here!
However, these new materials and structures still make for an impressive speed gain over traditional Silicon CMOS designs." (http://www.physorg.com/news3662.html)
Slashdot Mirror
Alice? Who the f**k is Alice?
Whoa.... Way back machine and Great Song! Haven't heard it forever... now I have to go find it :)
http://en.wikipedia.org/wiki/Living_Next_Door_to_Alice
At first glance, I thought the headline stated "Attempts to Court Linux Users Remain Pointless" and was confused... I wasn't sure where the news was in that statement.
Well, it was formatted nicely when I typed it out, I should have used the preview button, but being in a hurry to get my first post on slashdot done, I just hit submit, not noticing the posting type, so I apologize for the poor formatting.
;)
There are two quotes in my post, one from the first article and the other from a comment on the second article. I should have stated it was a users comment, but figured it would be fine as thats exactly what this forum is. For anyone who's interested enough to read these offtopic posts, now they'll know and my post will be formatted better next time
I just wanted to point that out, I think some posters are thinking about it incorrectly: "The 500 GHz mark was the goal when Feng and UI colleagues received a $2.1 million, five-year grant for the project from the Defense Advanced Research Projects Agency in October. In contrast, the transistors inside the central chip of a powerful personal computer run at around 50 or 100 GHz, Feng said. The fastest that such a chip runs as a package is currently around 3 GHz." http://www.news-gazette.com/news/local/2003/01/24/ fastest_transistor_made_at_ui/
In addition, University of Illinois broke 600 Ghz last year.
http://www.physorg.com/news3662.html
"The speeds quoted in this article are maximum rated *switching* speeds of a single transistor. Synchronous logic designs of the type found in microprocessors involve synchronous cells (known as flip-flops) and asynchronous gates providing boolean functions on the signals passing between flip-flops. The maximum rated frequency of any design is limited by the slowest path between flip-flops and this is what the clock signal will be set at.
As the paths between the clocked flip-flops are typically anywhere between 2 and 10 logic cells deep and with each one comprising 10's of transistors (usually in complementary configuration to aid switching speed), the overall figure for an ASIC design such as a uProcessor would be at least 2-4 times slower than the maximum transistor switching speed (it's not quite cumulative, because as one transistor starts switching, the voltage at the at the `gate' of the next one has already started changing causing it to start conducting, and so on). I also have a suspicion that there would be other real-world constraints such as cross-talk (noise between transistors) and thermal problems. I'd hazard a guess that a production-quality chip would be somewhere in the region of a tenth the speeds quoted here!
However, these new materials and structures still make for an impressive speed gain over traditional Silicon CMOS designs." (The speeds quoted in this article are maximum rated *switching* speeds of a single transistor. Synchronous logic designs of the type found in microprocessors involve synchronous cells (known as flip-flops) and asynchronous gates providing boolean functions on the signals passing between flip-flops. The maximum rated frequency of any design is limited by the slowest path between flip-flops and this is what the clock signal will be set at.
As the paths between the clocked flip-flops are typically anywhere between 2 and 10 logic cells deep and with each one comprising 10's of transistors (usually in complementary configuration to aid switching speed), the overall figure for an ASIC design such as a uProcessor would be at least 2-4 times slower than the maximum transistor switching speed (it's not quite cumulative, because as one transistor starts switching, the voltage at the at the `gate' of the next one has already started changing causing it to start conducting, and so on). I also have a suspicion that there would be other real-world constraints such as cross-talk (noise between transistors) and thermal problems. I'd hazard a guess that a production-quality chip would be somewhere in the region of a tenth the speeds quoted here!
However, these new materials and structures still make for an impressive speed gain over traditional Silicon CMOS designs." (http://www.physorg.com/news3662.html)