The implication of your original post was that AMD made a bad decision going for single-die quad core - a bad decision that has resulted in poor quad-core yields, poor enough that they have to "resort" to selling tri cores. Maybe I mistook your meaning, but everything else you've posted on this thread corroborates that implication. Anyway, I wanted you to back up your implication with some data (which I'm certain no one outside of AMD has), and instead you restated the obvious conclusion and made some analogy to a wet turd. Good job.
You can clearly see on page 3 (slide 6) that metal1 and metal3 are directly on top of each other. As I stated in a different post, you're confusing metal layer/wire routing in an IC with entire logic devices (transistors/gates/flops). Let me repeat it again for you: metal layers in an IC can cross.
No, I mean in a modern integrated circuit. Have you ever seen an IC layout in Cadence? There are anywhere from 7 to 10 layers of metal, and about that many layers of doped silicon or polysilicon or dielectric below the metal.
I think we're getting terminology mixed up. It's true that all the transistors/logic gates/flops are in a single "plane" which is made up of probably about 10 "layers" of Si, poly, and metal. Your 3D research is attempting to change how many "planes" of devices there are on a chip. However, wire routing in an IC, which is what the original question was about, can and does use many different metal layers, and traces definitely cross.
As I just posted below, there are around 10 metal layers in a modern IC, not a single plane. Traces can certainly cross one another on different layers.
We're talking about CPUs & AFAIK, the the traces can't cross one another.
There are around 10 metal layers in a modern IC. Traces can certainly cross one another on different layers.
Cpu 1 --> hop --> northbridge --> hop --> CPU 4 Or am I misunderstanding the definition of a "hop"?
I see what you're saying...but you're counting a processor interface as a hop. How many hops are there between cores in an Intel system then? CPU 1 --> hop --> front side bus --> hop --> CPU 4? No one counts hops that way. Your definition of hop would be like me saying there are two hops from your computer to your router, one between your processor and your network card over the PCI bus, and one between the network card and the router over ethernet.
Can you please provide a reference or link which contains yield data for AMD's quad-core parts? One which would support your assertion that they are seeing poor quad-core yields, poor enough that they are "recouping losses" by selling down-cored parts?
In theory with triple core, each processor is only 1 step away from the other processor (consider a triangular setup). With Quad core or greater there's either more bussing or more delays.
Firstly, for any general multi-node graph, it's entirely possible for three, four, eight, or any number of nodes to be only one hop away from each other. See fully-connected mesh. For the four-node case, imagine a 2D square, connected on the four sides, plus two links connecting the "diagonals" of the square. In that topology, each of the four nodes are only one hop away from each other. Of course, as the number of nodes increases, the cost of fully connecting them increases, as does the processing cost to multiplex and process transactions into the node from the (n-1) incoming links, but with only four nodes it's entirely possible to create a fully-connected network.
Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. What you're probably thinking of is a multi-socket system that only has two coherent links per socket - that would prevent you from making a fully-connected coherent interconnect for a 4-socket system.
Can you please provide a link or reference which states that there are 3-core Phenoms in development or production which have only 3 physical cores on the die, and that they are not just a down-cored version of the 4-core part?
AMD's multi-core processors use a fully-connected crossbar switch in the on-die northbridge to communicate. There is only one "hop" between each core.
What you're thinking of is a four-socket system whose interconnect network is not fully-connected - it's only the edges of a square, and there are two missing links between the "corners" of the square. That is certainly a legitimate topology for a four-socket system, with the limitation you pointed out (two hops to get to the opposite node), but it doesn't apply to AMD's quad-core die.
I don't think this is the case, but I'm throwing it out as a possibility: Is it possible that the definition of "purchase" has been changed to include you submitting to a search of your bag? Meaning, the purchase has not happened until a Circuit City employee searches the bag? In that case, Circuit City still maintains ownership of the bag and its contents and has a right to search them.
And if it's not, is it possible that the definition of "purchase" will be changed to include searching a bag?
What can the Linux movement do to curb the switchbacks, and address some of these concerns?
Exactly - FOSS advocates should be doing a lot of this. If a business loses a customer or sale, the sales team actually tries to figure out why the customer took their business elsewhere. This is almost certainly because money is involved, and losing customers is not good for the bottom line. If FOSS advocates started doing similar things, instead of making up excuses about Microsoft, or bitching about how "stupid" or "idiotic" people are for staying away from or leaving open-source software (see half the comments on this article), maybe we'd end up with better open-source software.
This really brings up a larger debate about the vices and virtues of capitalism (e.g. Microsoft) vs. communism (e.g. FOSS), but that debate can rage on for days.
The experts in the fields involved should be the ones to set standards, for instance scientists shoud set science standards, not politicans.
This is already how it works, but it recently got f'd up by the ID people. Experts write papers, which get peer reviewed and published in conferences and journals. After enough of the scientific community has accepted various theories, they get condensed into graduate-level survey courses, then undergraduate-level textbooks, and eventually filter down into high school textbooks and science experiments. This whole procedure was working fine until the ID folks demanded that their theory be taught in science classrooms without having gone through the above process. Putting it back the way that it was before the ID people got involved seems fine to me.
If a major engineering company employs clueless HR people who think "private" means "better", you probably don't want to work there. All the major engineering companies I've seen have highly competent HR folks, because hiring good people (both new college grads and experienced hires) is a competitive field in and of itself, and just as crucial to the success of the company as shipping quality products on time.
Yes, we know - there are eleven schools in the Big Ten. The conference logo even acknowledges it with an embedded "11" on either side of the "T". So please, no "OMG!!!!!!!11eleven" comments.
Of course she's hot, but she has a PhD from Harvard, and she's published a lot in major conferences. I'm pretty sure you can't get a PhD in CS, or papers accepted at major conferences (which are double-blind reviewed, btw) on looks alone.
As for this work, the article summary and the article itself are severely lacking in details. Go to the project page. And yes, people have been doing dynamic translation/optimization for years (Transmeta, Dynamo from HP - which she worked on actually, - rePLAY from UIUC), but it has always been with the intent to improve performance. This work is looking at a much wider scope of problems, and using the binary translation mechanism as a part of the solution. It looks to be in somewhat early stages - not sure specifically what problems they are looking to tackle other than the "dI/dt" problem that's posted on the project page. I'm interested to see what other papers come out of this group though.
Example: nglayout.initialpaint.delay as 0. This will slow rendering of the page as it causes reflows. Fools. From the article, just below the section on nglayout.initialpaint.delay:
Reduce the number of reflows
When Firefox is actively loading a page, it periodically reformats or "reflows" the page as it loads, based on what data has been received. Create a content.notify.interval integer preference to control the minimum number of microseconds (millionths of a second) that elapse between reflows. If it's not explicitly set, it defaults to 120000 (.12 of a second).
Too many reflows may make the browser feel sluggish, so you can increase the interval between reflows by raising this to 500000 (500,000, or 1/2 second) or even to 1000000 (1 million, or 1 second). If you set this value, be sure to also create a Boolean value called content.notify.ontimer and set it to true. Seems like setting nglayout.initialpaint.delay to 0 and bumping up the reflow interval can get you the page quicker and avoid too many reflows.
Ever see http://www.crhc.uiuc.edu/IMPACT/? They worked for about 10 years on compiler research targeting the Itanium and Itanium 2. Intel's own compiler is as good or better. The compiler research has been done.
Itanium and Itanium 2 can rock scientific, floating-point heavy applications with easy-to-determine memory access patterns (tight for loops and large arrays). But for general integer code (i.e. pointer chasing data structures like linked lists, trees, hash tables), all these compiler optimizations for an in-order architecture like Itanium are still worse than letting an out-of-order superscalar do its thing while an cache miss is being serviced. To compensate, Intel had to put 9MB of L3 on the Itanium die to hopefully make most datasets fit into the cache, but that turned out be expensive and unwieldy.
It's not that the compiler research wasn't there, it's that integer applications are a bitch for in-order processors.
I don't know much about solenoids. That said, is it possible to make a solenoid that acts in both directions (maybe by reversing the flow of current through the coil)? Failing that, could you hook up two solenoids to the valve, facing opposite directions? That way you'd have precise control over the opening and closing of the valve. Also, maybe a solenoid is faster acting than a spring, so that would improve things too.
What this amounts to is taking a part that is qualified to run at, say, 2.8GHz, and selling it with a default clock of 2.2GHz in order to meet TDP. Then, when one core is disabled, you crank up the other core's clock to 2.8GHz and stay within TDP.
This sounds like a good idea for mobile computing, since power (i.e. battery life) is by far the most important thing. But for servers, I think you'd want to sell as many chips as you can with the highest rated clock freq, since those are higher margin.
exactly what is stopping malware2.0 from killing my processor?
What is stopping malware1.0? If you're using a modern x86 CPU (by modern I mean Pentium Pro or K6 and later), those have a microcode patch capability that can be used to modify any microcoded x86 instruction. Lots of instructions are microcoded, especially system software instructions that your OS needs. Malware could install a patch that does nothing, or locks up, whenever your processor tries to execute a MOV CR3 instruction to change page tables. Even better, it could modify the BIOS to *always* install the patch, and then your system wouldn't even boot.
Of course you'd have to know the spec for microcode patches on Intel or AMD CPUs (which is NDA protected) and then get around whatever encryption, hashing, signing, etc. that Intel or AMD uses. But, I'm sure the same security measures would be in place for these proposed hardware patches as well.
But knowing that record companies use(d) die-hard fans like me to pay for such offensively vapid fare as fills the top 40 charts goes a long way toward easing my conscience about downloading files.
I can't stand reading this argument every time an article on the RIAA gets posted on Slashdot. I don't like them either, but this is adolescent logic (not to mention pretentious). And there goes my karma. Oh well.
Going to the theater, for me, is exactly what you said in the first sentence. I want other people to cook, bring me beer, watch the kids, and above all I want to go somewhere other than my living room. I don't want to make dinner, try to watch a movie with distractions all over the place, and then have to clean up later. It's an activity, something to do to get away from work and home. And if I can do that in an atmosphere that doesn't have sticky floors, screaming kids, and lets me eat reasonably good food that I didn't have to prepare, not to mention the beer, I would do it there. I'm proposing the Drafthouse as an alternative to regular theaters for the over-21 crowd that wants to go out to a movie. If you don't want to go out, then by all means downloading movies sounds great. But to me they seem like orthogonal problems.
I should have looked at the rest of your posts before assuming you were trolling. That's my mistake. Unfortunately, your mistake seems to be your belief that our society should behave like communism, in which artists don't require or desire any monetary compensation for their work. I don't believe it can, and I don't believe anyone should try it.
I started to compose a large counter-argument on intellectual property, but I decided to delete it. Arguing copyrights with someone of your beliefs quickly reaches stalemate because of fundamental lemmas that you believe to hold, which I don't.
Over 18 only, a full waitstaff to bring you food and beer while you enjoy the show, and plenty of mainstream, non-mainstream, and local movies. I don't go to regular theaters anymore since I moved to Austin and discovered the Drafthouses.
Slashdot Mirror
The implication of your original post was that AMD made a bad decision going for single-die quad core - a bad decision that has resulted in poor quad-core yields, poor enough that they have to "resort" to selling tri cores. Maybe I mistook your meaning, but everything else you've posted on this thread corroborates that implication. Anyway, I wanted you to back up your implication with some data (which I'm certain no one outside of AMD has), and instead you restated the obvious conclusion and made some analogy to a wet turd. Good job.
Before you call me incorrect, please take 2 minutes to look at some lecture notes from an intro VLSI course:
http://www.cse.sc.edu/~jimdavis/Courses/2005-Fall%20CSCE%20613/CSCE613-Week10-Chapter-04-05.pdf
You can clearly see on page 3 (slide 6) that metal1 and metal3 are directly on top of each other. As I stated in a different post, you're confusing metal layer/wire routing in an IC with entire logic devices (transistors/gates/flops). Let me repeat it again for you: metal layers in an IC can cross.
No, I mean in a modern integrated circuit. Have you ever seen an IC layout in Cadence? There are anywhere from 7 to 10 layers of metal, and about that many layers of doped silicon or polysilicon or dielectric below the metal.
I think we're getting terminology mixed up. It's true that all the transistors/logic gates/flops are in a single "plane" which is made up of probably about 10 "layers" of Si, poly, and metal. Your 3D research is attempting to change how many "planes" of devices there are on a chip. However, wire routing in an IC, which is what the original question was about, can and does use many different metal layers, and traces definitely cross.
As I just posted below, there are around 10 metal layers in a modern IC, not a single plane. Traces can certainly cross one another on different layers.
There are around 10 metal layers in a modern IC. Traces can certainly cross one another on different layers.
Cpu 1 --> hop --> northbridge --> hop --> CPU 4 Or am I misunderstanding the definition of a "hop"?I see what you're saying...but you're counting a processor interface as a hop. How many hops are there between cores in an Intel system then? CPU 1 --> hop --> front side bus --> hop --> CPU 4? No one counts hops that way. Your definition of hop would be like me saying there are two hops from your computer to your router, one between your processor and your network card over the PCI bus, and one between the network card and the router over ethernet.
Can you please provide a reference or link which contains yield data for AMD's quad-core parts? One which would support your assertion that they are seeing poor quad-core yields, poor enough that they are "recouping losses" by selling down-cored parts?
Firstly, for any general multi-node graph, it's entirely possible for three, four, eight, or any number of nodes to be only one hop away from each other. See fully-connected mesh. For the four-node case, imagine a 2D square, connected on the four sides, plus two links connecting the "diagonals" of the square. In that topology, each of the four nodes are only one hop away from each other. Of course, as the number of nodes increases, the cost of fully connecting them increases, as does the processing cost to multiplex and process transactions into the node from the (n-1) incoming links, but with only four nodes it's entirely possible to create a fully-connected network.
Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. What you're probably thinking of is a multi-socket system that only has two coherent links per socket - that would prevent you from making a fully-connected coherent interconnect for a 4-socket system.
Can you please provide a link or reference which states that there are 3-core Phenoms in development or production which have only 3 physical cores on the die, and that they are not just a down-cored version of the 4-core part?
AMD's multi-core processors use a fully-connected crossbar switch in the on-die northbridge to communicate. There is only one "hop" between each core.
What you're thinking of is a four-socket system whose interconnect network is not fully-connected - it's only the edges of a square, and there are two missing links between the "corners" of the square. That is certainly a legitimate topology for a four-socket system, with the limitation you pointed out (two hops to get to the opposite node), but it doesn't apply to AMD's quad-core die.
I don't think this is the case, but I'm throwing it out as a possibility: Is it possible that the definition of "purchase" has been changed to include you submitting to a search of your bag? Meaning, the purchase has not happened until a Circuit City employee searches the bag? In that case, Circuit City still maintains ownership of the bag and its contents and has a right to search them.
And if it's not, is it possible that the definition of "purchase" will be changed to include searching a bag?
Exactly - FOSS advocates should be doing a lot of this. If a business loses a customer or sale, the sales team actually tries to figure out why the customer took their business elsewhere. This is almost certainly because money is involved, and losing customers is not good for the bottom line. If FOSS advocates started doing similar things, instead of making up excuses about Microsoft, or bitching about how "stupid" or "idiotic" people are for staying away from or leaving open-source software (see half the comments on this article), maybe we'd end up with better open-source software.
This really brings up a larger debate about the vices and virtues of capitalism (e.g. Microsoft) vs. communism (e.g. FOSS), but that debate can rage on for days.
This is already how it works, but it recently got f'd up by the ID people. Experts write papers, which get peer reviewed and published in conferences and journals. After enough of the scientific community has accepted various theories, they get condensed into graduate-level survey courses, then undergraduate-level textbooks, and eventually filter down into high school textbooks and science experiments. This whole procedure was working fine until the ID folks demanded that their theory be taught in science classrooms without having gone through the above process. Putting it back the way that it was before the ID people got involved seems fine to me.
If a major engineering company employs clueless HR people who think "private" means "better", you probably don't want to work there. All the major engineering companies I've seen have highly competent HR folks, because hiring good people (both new college grads and experienced hires) is a competitive field in and of itself, and just as crucial to the success of the company as shipping quality products on time.
Yes, we know - there are eleven schools in the Big Ten. The conference logo even acknowledges it with an embedded "11" on either side of the "T". So please, no "OMG!!!!!!!11eleven" comments.
As for this work, the article summary and the article itself are severely lacking in details. Go to the project page. And yes, people have been doing dynamic translation/optimization for years (Transmeta, Dynamo from HP - which she worked on actually, - rePLAY from UIUC), but it has always been with the intent to improve performance. This work is looking at a much wider scope of problems, and using the binary translation mechanism as a part of the solution. It looks to be in somewhat early stages - not sure specifically what problems they are looking to tackle other than the "dI/dt" problem that's posted on the project page. I'm interested to see what other papers come out of this group though.
When Firefox is actively loading a page, it periodically reformats or "reflows" the page as it loads, based on what data has been received. Create a content.notify.interval integer preference to control the minimum number of microseconds (millionths of a second) that elapse between reflows. If it's not explicitly set, it defaults to 120000 (.12 of a second).
Too many reflows may make the browser feel sluggish, so you can increase the interval between reflows by raising this to 500000 (500,000, or 1/2 second) or even to 1000000 (1 million, or 1 second). If you set this value, be sure to also create a Boolean value called content.notify.ontimer and set it to true. Seems like setting nglayout.initialpaint.delay to 0 and bumping up the reflow interval can get you the page quicker and avoid too many reflows.
Itanium and Itanium 2 can rock scientific, floating-point heavy applications with easy-to-determine memory access patterns (tight for loops and large arrays). But for general integer code (i.e. pointer chasing data structures like linked lists, trees, hash tables), all these compiler optimizations for an in-order architecture like Itanium are still worse than letting an out-of-order superscalar do its thing while an cache miss is being serviced. To compensate, Intel had to put 9MB of L3 on the Itanium die to hopefully make most datasets fit into the cache, but that turned out be expensive and unwieldy.
It's not that the compiler research wasn't there, it's that integer applications are a bitch for in-order processors.
I don't know much about solenoids. That said, is it possible to make a solenoid that acts in both directions (maybe by reversing the flow of current through the coil)? Failing that, could you hook up two solenoids to the valve, facing opposite directions? That way you'd have precise control over the opening and closing of the valve. Also, maybe a solenoid is faster acting than a spring, so that would improve things too.
Just some thoughts.
What this amounts to is taking a part that is qualified to run at, say, 2.8GHz, and selling it with a default clock of 2.2GHz in order to meet TDP. Then, when one core is disabled, you crank up the other core's clock to 2.8GHz and stay within TDP. This sounds like a good idea for mobile computing, since power (i.e. battery life) is by far the most important thing. But for servers, I think you'd want to sell as many chips as you can with the highest rated clock freq, since those are higher margin.
What is stopping malware1.0? If you're using a modern x86 CPU (by modern I mean Pentium Pro or K6 and later), those have a microcode patch capability that can be used to modify any microcoded x86 instruction. Lots of instructions are microcoded, especially system software instructions that your OS needs. Malware could install a patch that does nothing, or locks up, whenever your processor tries to execute a MOV CR3 instruction to change page tables. Even better, it could modify the BIOS to *always* install the patch, and then your system wouldn't even boot.
Of course you'd have to know the spec for microcode patches on Intel or AMD CPUs (which is NDA protected) and then get around whatever encryption, hashing, signing, etc. that Intel or AMD uses. But, I'm sure the same security measures would be in place for these proposed hardware patches as well.
I can't stand reading this argument every time an article on the RIAA gets posted on Slashdot. I don't like them either, but this is adolescent logic (not to mention pretentious). And there goes my karma. Oh well.
Going to the theater, for me, is exactly what you said in the first sentence. I want other people to cook, bring me beer, watch the kids, and above all I want to go somewhere other than my living room. I don't want to make dinner, try to watch a movie with distractions all over the place, and then have to clean up later. It's an activity, something to do to get away from work and home. And if I can do that in an atmosphere that doesn't have sticky floors, screaming kids, and lets me eat reasonably good food that I didn't have to prepare, not to mention the beer, I would do it there. I'm proposing the Drafthouse as an alternative to regular theaters for the over-21 crowd that wants to go out to a movie. If you don't want to go out, then by all means downloading movies sounds great. But to me they seem like orthogonal problems.
Maybe you are trolling here - I said "fundamental lemmas", not "fundamentalist lemmas". There's no religious fanatic connotation to the first.
I started to compose a large counter-argument on intellectual property, but I decided to delete it. Arguing copyrights with someone of your beliefs quickly reaches stalemate because of fundamental lemmas that you believe to hold, which I don't.
http://www.drafthouse.com/
Over 18 only, a full waitstaff to bring you food and beer while you enjoy the show, and plenty of mainstream, non-mainstream, and local movies. I don't go to regular theaters anymore since I moved to Austin and discovered the Drafthouses.