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30% chance

Bah! You spoiled my explanation by explaining it properly :)

The number (30%) is referred to as the quantum efficiency. CCD sensors have higher QE than CMOS because they have a larger percentage of the pixel that is light sensitive (higher fill factor).

I'm not sure I agree with you here. My understanding is that QE is the chance that a photon hitting the light sensitive area will generate an electron-hole pair. The fill factor is nothing to do with it, but still important of course. As it is, 30% is widely used as "the" QE for a standard CMOS process - it wouldn't be possible to quote that without also specifying the fill factor if it depended on fill factor. A better reasoning - the unit for QE is A/W - no mention of area there. It's also true that there are camera optimised CMOS processes that offer improved QE - for instance the AMS C35B4 OPTO process which is a drop in replacement for their C35B4C3 process - change from "small" QE to "not quite as small QE" without modifying the design. Alas, I have no data on the opto process but I think that it offered a QE of 40%. CCDs work on the same principle - they are for cameras so the process is optimised to give higher QE.

longer wavelengths will generate electron-hole pairs too deep in the silicon to be captured.

The corollary of Moore's law is perhaps that the feature size will halve every however often it was that he said - so it does have some effect. What some people don't know is that as the x and y feature sizes shrink, so does the z - although not necessarily as rapidly. As you say the z dimension affects the wavelength sensitivity, so by shrinking it we'll be reducing the ability to detect longer wavelengths. I'm sure that this is one reason why processes like the 0.35um one I mention above is still in wide use in camera research whilst most people here would scoff at the very idea that anybody was using such an "archaic" technology. Going from that 0.35um process to the UMC 0.18um process and the depth of the N-well junction just about halves. Price and ooh, some headroom in analogue design are other reasons for using such a process of course.

Roger

30% chance

Bah! You spoiled my explanation by explaining it properly :)

The number (30%) is referred to as the quantum efficiency. CCD sensors have higher QE than CMOS because they have a larger percentage of the pixel that is light sensitive (higher fill factor).

I'm not sure I agree with you here. My understanding is that QE is the chance that a photon hitting the light sensitive area will generate an electron-hole pair. The fill factor is nothing to do with it, but still important of course. As it is, 30% is widely used as "the" QE for a standard CMOS process - it wouldn't be possible to quote that without also specifying the fill factor if it depended on fill factor. A better reasoning - the unit for QE is A/W - no mention of area there. It's also true that there are camera optimised CMOS processes that offer improved QE - for instance the AMS C35B4 OPTO process which is a drop in replacement for their C35B4C3 process - change from "small" QE to "not quite as small QE" without modifying the design. Alas, I have no data on the opto process but I think that it offered a QE of 40%. CCDs work on the same principle - they are for cameras so the process is optimised to give higher QE.

longer wavelengths will generate electron-hole pairs too deep in the silicon to be captured.

The corollary of Moore's law is perhaps that the feature size will halve every however often it was that he said - so it does have some effect. What some people don't know is that as the x and y feature sizes shrink, so does the z - although not necessarily as rapidly. As you say the z dimension affects the wavelength sensitivity, so by shrinking it we'll be reducing the ability to detect longer wavelengths. I'm sure that this is one reason why processes like the 0.35um one I mention above is still in wide use in camera research whilst most people here would scoff at the very idea that anybody was using such an "archaic" technology. Going from that 0.35um process to the UMC 0.18um process and the depth of the N-well junction just about halves. Price and ooh, some headroom in analogue design are other reasons for using such a process of course.

Roger

I'm a bit out of it on the latest design requirements for CPUs - is the technology of these folks actually good enough to make a reasonably modern CPU?

Open hardware, on the other hand, is useful only for education or simulations unless you happen to have a fab plant.

How can you NOT know about this:

http://www.mosis.org/

If you want to attempt it, MOSIS does small run fabrication by batching up small runs onto a single wafer and running them through commercial fabs like IBM and TSMC. The prices aren't out of reach.

However, you should remember from the VLSI class you've taken that it may take several runs before getting anything usable. Unless your design has some aspect that makes using a FPGA infeasible, you'd probably be better off with the FPGA. As I recall, a couple of FPGA vendors can also do conversions from FPGAs to hard-wired ASICs if you desire it later.

If you want to attempt it, MOSIS does small run fabrication by batching up small runs onto a single wafer and running them through commercial fabs like IBM and TSMC. The prices aren't out of reach.

However, you should remember from the VLSI class you've taken that it may take several runs before getting anything usable. Unless your design has some aspect that makes using a FPGA infeasible, you'd probably be better off with the FPGA. As I recall, a couple of FPGA vendors can also do conversions from FPGAs to hard-wired ASICs if you desire it later.

Even going with 130 nm technology (which is already "outdated") can cost a million dollars just for the masks. Yield, packaging, and other issues can easily push up the costs to several times that.

I'm a bit skeptical about that. We run 0.25um stuff here all the time, 5 layer metal, and the mask cost numbers I've heard are in the $100k range for a dedicated production mask. Shuttle costs are well below that (depending if your fab of choice runs shuttles and you can get on them). I just checked MOSIS and it looks like 0.13um on an IBM 8RF process seems to be in the $6k to $50k range for 40 parts (based on die size - assuming I read their numbers correctly).

Now tools on the other hand are a different matter. Layout, synth, and place-and-route tools can be -very- spendy. One could use Magic for layout (I don't know if it supports place and route though).

Package wise I would use some sort of quad flat package for prototypes. BGAs are a pain when it comes time for evaluation - you would need some sort of reflow oven to stick it to the board, and then forget about probing pins.

"now if i somehow got a hold of a schematic for my processsor and managed to improve the design, how would i go from paper to silicon?"

Assuming you can come up with the cad tools to implement your schematic and layout changes, you can use MOSIS to fab the chip. It costs money, but getting hardware for free as in beer is unrealistic.

Why would you ever want to buy a fab? Forget that unless you plan on running a chip business. For working on a prototype you need to check out MOSIS. They might do low volume production also - I never checked into it.

I fab'ed my MS thesis project through MOSIS. Die area was approx 3.7mm square in 0.5um CMOS, and it cost about $3000 for 25 samples. Worked great. If I was ever going to do another private project I would go that route.

Why can't an individual outsource too?

You can. Check out MOSIS. They will fab chips on one of several different fab lines for a reasonable price. For example, it cost about $8000 for 25 3mm by 3mm chips in 0.5 micron.

Prototyping can be done much cheaper through MOSIS. If you just want to play with a simple processor (say an 8 bit processor in the 0.5 micron process) you can get in the game for $5,900 US. If you want to play in a 32-bit world, but don't need the hottest process, big onboard cache, etc., consider $15,500 US for 40 parts in a 0.25 micron TSMC process.
In amy case, the real advantage to a roll-your-own processor is not to build a better general purpose processor better than P4/SPARC/ARM/MIPS/PPC but to create a special purpose processor that does the one thing you care most about very well.

Prototyping can be done much cheaper through MOSIS. If you just want to play with a simple processor (say an 8 bit processor in the 0.5 micron process) you can get in the game for $5,900 US. If you want to play in a 32-bit world, but don't need the hottest process, big onboard cache, etc., consider $15,500 US for 40 parts in a 0.25 micron TSMC process.
In amy case, the real advantage to a roll-your-own processor is not to build a better general purpose processor better than P4/SPARC/ARM/MIPS/PPC but to create a special purpose processor that does the one thing you care most about very well.

Prototyping can be done much cheaper through MOSIS. If you just want to play with a simple processor (say an 8 bit processor in the 0.5 micron process) you can get in the game for $5,900 US. If you want to play in a 32-bit world, but don't need the hottest process, big onboard cache, etc., consider $15,500 US for 40 parts in a 0.25 micron TSMC process.
In amy case, the real advantage to a roll-your-own processor is not to build a better general purpose processor better than P4/SPARC/ARM/MIPS/PPC but to create a special purpose processor that does the one thing you care most about very well.

Actually, you can get short-run IC fabrication for a reasonable price. Check out the MOSIS website, they will do fabrication runs of 25 chips or so. For a price example, we did a 3mm by 3mm chip in 0.5 micron Agilent (HP-14B), that cost about $8000 for 25 chips, all packaged. If you are a university student, you may be able to get fabrication donated, so you might want to check that out. I've had one chip made through this program. (It's a PIC16C6x compatible microcontroller, for those interested.) And if you want a layout tool, there is a freely available program called MAGIC that can handle this task (sorry too lazy to find link).

Actually, you can get short-run IC fabrication for a reasonable price. Check out the MOSIS website, they will do fabrication runs of 25 chips or so. For a price example, we did a 3mm by 3mm chip in 0.5 micron Agilent (HP-14B), that cost about $8000 for 25 chips, all packaged. If you are a university student, you may be able to get fabrication donated, so you might want to check that out. I've had one chip made through this program. (It's a PIC16C6x compatible microcontroller, for those interested.) And if you want a layout tool, there is a freely available program called MAGIC that can handle this task (sorry too lazy to find link).

Mosis? Should be only a few 10's of K to get a batch of your favourite CPU whipped up.

The natural question for many /.'ers that also participate in distributed.net is whether or not this will be useful for crunching keys.

I'm guessing, in it's base form, the device is tuned for (en|de)crypting large volumes of data with a fixed key, and that key reloads are expensive. Translation: It won't help a d.net-style keysearching effort much as-is.

Does anyone have more information on this to confirm or deny this conjecture?

Also, is anyone out there crazy enough (and skilled enough w/ VHDL) to hack this device into the world's fastest RC5 block cruncher? :-) Places like MOSIS will fab "educational" and "prototype" designs in small quantities for reasonable prices.