Design Your Very Own Microprocessor

LightJockey writes: "CircuitCellar has a great article on designing and building your own microprocessor using FPGAs and openly available processor designs, ranging from ARM and MIPS based to custom designs, and even a couple SPARC based chips, and also a really cool 'processor toaster,' start with a base processor design, and using a webpage to select upgraded components, it spits out the VHDL file you need to create it. Brings garage hackerdom up to a whole new level!"

Comments

Processor toaster?

[AlaskanUnderachiever]

That's nothing new. I've been toasting processors for years now. All you need is any AMD chip, a failed heat sink, and 30 seconds of Half Life.

Re:Processor toaster?

[TNT_JR]

Well, since this one seems to be going off-topic from the very start...

You are one UNLUCKY dude! I have never heard of a heatsink failing, but you have seen this multiple times? What is the most common failure mode of aluminum heatsinks? :)

Re:Processor toaster?

[cperciva]

In my experience, Half Life is not necessary.

Re:Processor toaster?

[Merlin42]

I actually had a 'heatsink failure' once, thankfully it happened before I had finished setting up the machine so nothing died. The mode of failure was that one of the plastic clips that the retention mechanism connects to bent. It was on a very old MOBO so I just tossed it rather than try toasting chips. Theoretically I could see this cheap bit of plastic failing during operation.

Re:Processor toaster?

[TNT_JR]

Nope. That was a failure of the 'retention mechanism', *not* the heatsink? ;)

Re:Processor toaster?

[PD]

What is the most common failure mode of aluminum heatsinks?

Temporary suspension of the black body radiation law.

Re:Processor toaster?

[MoneyT]

One would assume that the retention mechanism of the heatsink would be a part of the unit as a whole, therefore, the heatsink failed.

Re:Processor toaster?

[MoneyT]

Not only is it not new, it's no longer a Hobby. My self and my firends hire our processor toasting services to disgruntled computer convention attendies pissed at the peopl esucking prescious bandwidth with their counterstrike server.

One subtly toasted processor + failed server for $20. And since they're all rent-a-sys type computers, no one really cares

Re:Processor toaster?

[sean23007]

It takes you 30 seconds? I'm much more efficient than that, it takes me only 15 seconds. Then again, I use my Whole Life, so it balances out...

Re:Processor toaster?

[Anonymous Coward]

halflife sucks

Re:Processor toaster?

[Anonymous Coward]

q2 > halflife

Re:Processor toaster?

[TNT_JR]

NAK to that too. That's like saying the lugnuts are part of the wheel? Heatsinks are just as easily mounted with thermal epoxy.

The whole issue is kind of funny since *real* processors have die-temperature sensors and any decent design would use these to prevent damage.

Who's gonna make a pun (intentional or not) on the term 'die-temperature' and drive this fork even *more* off-topic? :)

Re:Processor toaster?

[Anonymous Coward]

> I have never heard of a heatsink failing

What cave have you been living in? AMD processors are notorious for this. Heat sink fails = you just bought a new processor (and possible mainboard). Simple math. Are AMD processors really worth the cheaper price considering this? Intel processors underclock themselves before they overheat. I like to think of the extra cost of an Intel processor as the cost of insurance.

And don't even get me started on stability...

Re:Processor toaster?

[Anonymous Coward]

pitfall > q2

Re:Processor toaster?

[Anonymous Coward]

duck hunt > pitfall

Re:Processor toaster?

[Dwonis]

And don't even get me started on stability...

Is this really the processor's fault? I was always under the impression that it was the cheap VIA motherboards that caused this.

Re:Processor toaster?

[Dwonis]

pong = {}

Re:Processor toaster?

[Dwonis]

Bah. HTML entities...

pong {}

Re:Processor toaster?

[MoneyT]

real processors did, but lots of early ones didn't. The really early intel processors, before the 8080s had a fatal design flaw in which a certain series of since lost commands entered into the computer had the wonderful effect of overloading and overheating the processor.

home grown processors?

[Jacer]

just imagine a a cluster of these!

Don't allow whoever designed emacs to get ahold ..

[linzeal]

The damn thing would incorporate circuitry for a garage door opener, a missile guidance system, and would have all 20 megs of emacs stored in microcode.

YASPR

[MrHat]

1. Create VHDL from 'processor toaster', and take it into the garage on a CD-R.
2. ...
3. Profit!

Hell, someone had to do it. If you guys have some spare chip fabrication equipment in your garage, can I borrow it?

Re:YASPR

[Anonymous Coward]

1.Create VHDL from 'processor toaster', and take it into the garage on a CD-R.
2.... ---------- A MIRACLE OCCURS HERE
3.Profit!

Re:YASPR

[NoMoreNicksLeft]

Aren't you supposed to say this in haiku or limerick form?

Besides, if AMD discovers that you've stole their trade secrets, they'll sue you into the ground.

Re:YASPR

[Anonymous Coward]

There's a variety of programming boards out there that can program a chip to your specs given the VHDL file. Just check out what Altera has to offer.

Re:YASPR

[fliptout]

Uhh, I think he was making a Southpark reference...

Amateur chip designers

[ObviousGuy]

Without training and experience in hardware design at the college level, it is doubtful that any amateur could come up with a design that improved on existing chip designs or create a fundamentally new design that would be of interest to chip companies.

The hope springs eternal, though.

Re:Amateur chip designers

[s20451]

Yes, but could thousands of amateurs, many with college degrees, work on a distributed project to design microprocessor that improves on existing commercial models, a la Linux? (Maybe the article talks about this, but it's slashdotted.)

Re:Amateur chip designers

[inkyfellow]

I just think that it is interesting how this wouldn't have been possible until recently. The expense involved in chip making plants is making chip manufacturers different companies than designers. The designers then outsource the manufacturing to the plants.

Why can't an individual outsource too? The beauty of all this is that an individual can. Even though the plant may have large sunk costs involved, the cost of making an individual chip may get to the point where people really can design their own advanced chips.

Hey, perhaps we'll have Open Source chip designs that'll be traded online. Then we'll have an entire machine based on completely open standards.

That'll be hot.

Re:Amateur chip designers

[dfn5]

It is not about designing a chip that you could sell to another company. It is about the home electronic hobbyist. I remember reading Circuit Cellar in Byte magazine a decade ago. It was always cool to sit down at your bench with a bread board and a collection of parts from Radio Shack and do it yourself. I'm glad Circuit Cellar is still alive and kicking.

Re:Amateur chip designers

[Oizoken]

i had those lessons in univ from someone who designed computer chips, and even now it's probably impossible for us univ students to come up with a better cpu design than those around, i just guess people really need to deepen themselves in the subject and follow the curren t cpu design (maybe even work at amd/intel/sparc/transmeta) to get enough background, before comming up with a truly better design.

Re:Amateur chip designers

[tius]

Actually, this has been possible for a long time (i.e. 10 years or so). The only differences now are that there are single FPGA chips that can accomodate the entire design, and that there are also some fairly mature Open Source cores available.

Re:Amateur chip designers

[cyr]

Silicon is only cheap if you make *many* copies of the same chip.

However, you can design something in VHDL and put it into a CPLD och FPGA chip (programmable logic).

BTW, check out www.opencores.org and similar sites. There are already a number of open source "chip designs" available, in the form of VHDL or Verilog source code.

Re:Amateur chip designers

[mrm677]

Designing a modern microprocessor can not be done by amateurs or a group of people with a B.S. degrees in electrical engineering. Sure, many of us have taken undergraduate architecture classes and maybe have designed a simple pipelined microprocessor in Mentor Graphics or VHDL/Verilog. Some of us maybe even implemented it with FPGAs.

However, anything close to being as complex as Intel/AMD chips requires an army of highly experienced architects/engineers with many of them having pHD's. Even the software design tools, such as Mentor, cost well over $100,000

Then building the chip is another beast requiring a fab facility in the order of $1 billion for any process with feature sizes smaller than 0.5.

Microprocessors are becoming so complex to design and build, that only a few companies are surviving. Sort of like the aircraft industry. There are only 2 remaining companies in this world that design and build 300+ passenger commercial aircraft (Boeing and Airbus). It is infeasible for a new competitor to arise because of the capital involved (unless of course it is nationally sponsored).

Re:Amateur chip designers

[svirre]

Sure you can outsource. Practically all design houses outsorce fabbing (current estimates indicate that you need a turnaround of approx $7 billion to justify your own fab)

As a small time operator no fab is going to talk to you however. You are going to go through a middleman (just as well since these often supply design services like P&R(Place and route) and synthesis, withouth these services you'll be looking at a investment at approx $200 000 in tools)

For a pure digital diesign you can then get away with a tool investment of $2-5000 for simulation.

For fabbing you should expect $20-50000 in expenses to ready your design for tape-out. The cost of the manufacture will depend of wether you are going for an engineering run of MPW (Multi Project Wafer). An MPW will cost you $10-100 000 depending on process sophistication and size and yield 10-200 chips. An engineering run requires a dedicated mask set which will cost $100-500 000. The engineering run itself is consisderably cheaper and the masks may be reused for manufacture.

If you are going to do any leading edge design you will however need to do your own synthesis and P&R. If you target 0.18um of better you propably are going to need som degree of physical synthesis capability ($100000 and up). Fo manufacture you will also need to prepare a test procedure (ATPG tools (Automatic Test Pattern Generator) check in at approx $100000)

Also remeber that all tools will usually require a maintenance fee of 10-20% annually of purchase price (pays for upgrades and support)

At last don't forget computer hardware to run your tools on. Linux suffices for most tools, but some will only run on Sun/HP workstations.

Re:Amateur chip designers

[Anonymous Coward]

that's the problem though. practically anyone can code, its a monkeys job most of the time. whereas chip design takes real engineers, people with real talent.

Re:Amateur chip designers

[Bobzibub]

Replace
'Microprocessor' with 'Operating System'
'Intel' with 'Microsoft'
'AMD' with 'Sun'
....
Read the above comment again. ; )


Building a chip in a fab would have to be a traditional commercial endevour. Agreed. Aren't Boeing and Airbus the only two airline manufacturers because they are subsidized and therefore others cannot compete? Cheers!

Re:Amateur chip designers

[MoneyT]

I could swear I read something about this being the reaction Steve & Steve got from people about home computers. Too complex to buid a useful computer, never be able to compete with the big guys. Guess they were wrong too.

Besides, I wouldn't be aiming to build a computer processor. I'd just wna tto build a processor that could process something.

Re:Amateur chip designers

[Anonymous Coward]

STFU you zealous fool.

Re:Amateur chip designers

[imnoteddy]

Prototyping can be done much cheaper through MOSIS. If you just want to play with a simple processor (say an 8 bit processor in the 0.5 micron process) you can get in the game for $5,900 US. If you want to play in a 32-bit world, but don't need the hottest process, big onboard cache, etc., consider $15,500 US for 40 parts in a 0.25 micron TSMC process.
In amy case, the real advantage to a roll-your-own processor is not to build a better general purpose processor better than P4/SPARC/ARM/MIPS/PPC but to create a special purpose processor that does the one thing you care most about very well.

Re:Amateur chip designers

[MMMMMMMMMMMMMMMMMMMM]

Who built a 300+ passangers aircraft in his backyard just for fun? Name one!

Re:Amateur chip designers

[mav[LAG]]

I agree with most of your points but the ARM is an interesting counter-example. It was designed by four or five guys at Acorn Computers in the UK. They had just been told to sod off by Intel when they wanted to license the 8086 as a base design. It took about five man years of work - five guys working for just under a year - everything worked first time when plugged in (including all the IO and the peripherals), and they got around the manufacturing problem by licensing the design to OEMs who wanted to embed it. It was (and is) a joy to program for, has very low power consumption and is easily extensible.

In a supreme irony, Intel ended up licensing the ARM from Acorn RISC machines in the early 90s. Right now ARMs are everywhere - PDAs, cellphones, routers and switches. Now of course a 200Mhz ARM running in an iPAQ is a little less complex than a modern P4 with SSE 2 and all its other bells and whistles, but it's close. I think its encouraging that designing a successful microprocessor has been shown to be not solely the domain of giant corporations with billions of dollars in fabs and armies of PHD-wielding staff.

Re:Amateur chip designers

[selectspec]

It is infeasible for a new competitor to arise because of the capital involved.

That's not true actually. The costs of design (not manufacture) are coming way down as simulation and development technologies streamline the design process. There is heavy competition in the microprocessor space for servers and networking chips. Intel and AMD's strangle hold on the PC and general server market is due to the overwelming developer support of the x86 platform, not the costs of developing new chips. Look at the Itanium. If it wasn't for the x86-64 they wouldn't be able to sell one of them. If you look at the embedded space, where developer support is less relevant, you'll see a wide spectrum of chip makers and healthy competition.

Re:Amateur chip designers

[raytracer]

Designing a modern microprocessor can not be done by amateurs or a group of people with a B.S. degrees in electrical engineering. Sure, many of us have taken undergraduate architecture classes and maybe have designed a simple pipelined microprocessor in Mentor Graphics or VHDL/Verilog. Some of us maybe even implemented it with FPGAs.

This is either irrelevant or just stupid, depending on how you look at it,

It is true that no amateurs are going to build their own 747 either, but there are no lack of people who build their own planes and gliders. Using FPGAsof modest cost, amateurs can implement processors which are perhaps 8 years back in the power curve. I don't know about you, but I found the computer that I owned 8 years ago to be quite a useful gadget. The ability to reprogram the core of your microprocessor to (say) add new instructions, peripherals and capabilities seems to be a cool one. As the FPGA industry moves forward, experimenters in this technology will also track Moore's law improvements. Yes, they will always be behind what billion dollar fabs can produce, but I fail to see why this is a problem for amateur chip designers.

Microprocessors are becoming so complex to design and build, that only a few companies are surviving. Sort of like the aircraft industry. There are only 2 remaining companies in this world that design and build 300+ passenger commercial aircraft (Boeing and Airbus). It is infeasible for a new competitor to arise because of the capital involved (unless of course it is nationally sponsored).

Again, so what? We were talking about amateur designs, not going into competition with Intel and AMD. I imagine that Linus heard similar arguments about the infeasibility of writing his own operating system.

Linus took the wide availability of inexpensive PC computers and leveraged those to create a new operating system. Amateur FPGA designers could try to leverage the availability of inexpensive FPGA chips to design their own processors. If you asked me the likelihood that anyone would be using them in a commercial environment a year from now, I'd say it was pretty low, but in a ten year time span....

Re:Amateur chip designers

[mrm677]

ARM is really an instruction set specification. Most ARM implementations I know of are rather simple (except for the engineering expended to make them low-power).

I can't think of an ARM implementation that is superscaler, speculative, and performs out-of-order execution.

Re:Amateur chip designers

[mrm677]

Very true about the embedded space...lots of competition. Embedded processors are actually very simple cores. They are usually in-order and have simple pipelines. Plus there exists a large design space of customization that stimulates competition and offers many different companies the ability to offer something different. Just look at all the different "systems on a chip" out there.

And yes, standard tools exist that can automatically transform high-level specifications into mask-level designs. However, for anything that will come close to the price/performance ratio that Intel and AMD have achieved for general-purpose microprocessors, full custom design is usually required.

Re:Amateur chip designers

[svirre]

I was assuming at least 0.35um.

These prices are however just for the fabrication, no?

If so you will still need to do synthesis and P&R.

Of cource your point about just dropping in a processor as beeing uninteresting is well taken. Indeed a CPU is a very inefficient piece of logic. Dropping CPUs in FPGAs seem to me as a particularly stupid thing to do.

The whole reason many want a CPU in a SoC product is that they want the flexibility to reconfigure the chip and update it's algorithms without having to fabricate a new device. On a FPGA you allready have the flexibility to update at any time at practically no cost, so on those you will want to forgo the CPU entirely and implement the algorithm completely in hardware.

Also since FPGAs generally are unable to reach high clockspeeds, the designer really need to paralellize his algorithm to achieve any kind of performance.

(We recently have done a SoC project which was to be prototyped in a FPGA which included a 16 bit single issue unpipelined RISC core. On a virtex II 3000-4 this achieved a speed of 18MHz max)

Re:Amateur chip designers

[Anonymous Coward]

That's a good one. Hardware designers with talent have real jobs. From the looks of the comments most /. weenies can design simple little MCU's with few instructions that only work in simulation.

Though it'll be really funny to watch.

Re:Amateur chip designers

[HeyLaughingBoy]

Replace
'Microprocessor' with 'Operating System'
'Intel' with 'Microsoft'
'AMD' with 'Sun'
....
Read the above comment again. ; )

Just because you can claim that other complex products have been created by people with fewer resources, does not invalidate the original post. The cost of entry into the software market is HUGELY less than entry into hardware. Within hardware design, there are many fields where the bar to entry is very low (simple Data Acquisition/Control interfaces come to mind) and many amateurs are selling commercial products. But most of the high-end stuff requiring expensive tools is beyond the reach of the guy in the garage. I guess my point is that, to take Linux as an example, you can write a kernel and have it be immediately useful. Heck,I've done this by writing a small preemptive RTOS kernel for my own use. But simply building, say, a pipelined arithmetic processing unit gets you nothing without the rest of the CPU around it.
There are many areas in electronics where those of us struggling in the basement can build high-performance equipment, but CPU design is not one of them.

Apples and onions, dude.

Re:Amateur chip designers

[_Knots]

FPGA - Field Programmable Gate Array (also FPLGA - Field Programmable Logic Gate Array).

These neat chips have the wonderful feature of turning *software* into hardware. They take a bitsequence (much like... uh... oh yeah, object code!) and rewire themselves on the fly. Some chips can even do ~10 complete reprogrammings per second. They also come in various degrees of "fineness" - some give you individual gates (not, and, or, xor, etc.) while others give you computational or other large units (multiplier, adder, memory, I/O bus). I dunno if any give the "best of both worlds" but it would not be hard to glue a handful of FPGAs together, one that handled IO, one that was the reprogrammable cruncher, etc.

So it's certainly possible to design chips, just as one codes. And, hey, if the design doesn't work, it's not like you cooked a chip - keep a "known-good" (or good-enough =) version in a serial FLASH or battery-backed serial (static) RAM chip and program out to another battery-backed serial (static) RAM chip. Design some trivial (read: the simplest case is just a DPST switch) hardware to pick which chip gets read at bootup, and *bang* back in business.

Sounds promising. Maybe somebody should offer kits of interwired FPLGAs and the necessary program-storage chips. Would be interesting to port Linux to such a computer (augmented, obviously, with interfaces - like USB [storage, sound, networking], FDD [bootstrapping the Linux kernel to then get at the USB stuffs], and some form of a video console [prolly serial at first]) The interface glue would be difficult but not prohibitively so. And all it takes is one person to publish the designs. Conveniently, there are many off-the-shelf chips with well-available specs for USB host and device support (Phillips makes some, for instance), FDDs have been around so long that I'm sure the chips are there for cheap, and serial, well, I'm sure some FPGAs have serial I/O on them, and if not, oh well, it's easy to do in hardware (shift registers, clock generator, done).

Hey, just occurred to me. Asynchronus computing is becoming more and more discussed as central CPU clocks reach "terminal velocity." An array of FPGAs would be a *great* way to do coarse-grained async computing.

-Knots

Re:Amateur chip designers

[HeyLaughingBoy]

There are many areas in electronics where those of us struggling in the basement can build high-performance equipment, but CPU design is not one of them.

Posted too soon. that last phrase should read, "but modern, high-performance CPU design is not one of them"
I am well aware that many people build simple CPUs at home. I know someone who did it 20+ years ago with TTL chips!

Re:Amateur chip designers

[QuantumFTL]

Designing a modern microprocessor can not be done by amateurs or a group of people with a B.S. degrees in electrical engineering. Sure, many of us have taken undergraduate architecture classes and maybe have designed a simple pipelined microprocessor in Mentor Graphics or VHDL/Verilog. Some of us maybe even implemented it with FPGAs.

That's a very misleading statement, as you define MODERN as meaning something bloated and complex like AMD/Intel chips. The problem isn't that making a MODERN processor is very difficult, it's that implementing a poorly designed ISA is. If you insist on using x86 (I would *NEVER* make an x86 processor on my life) then of course you'll never get anywhere. I do not think, however, that it would be that difficult to make a full MIPS R2000 chip, ala Nintendo 64. Most MIPS instructions are very simple to implement, it becomes mostly an issue of pipeline control, and then caching/memory interfacing. I will grant that the designing of an FPU from scratch would be somewhat difficult (the MIPS processor I designed lacked an FPU, so I have not done that). MIPS, or heck even a PowerPC chip would not be prohibitively complex. There's no future in CISC, and I do not see why you choose to use that as your metric for determining feasability. RISC chips are really not all that complex (depends on how many execution units you want, etc) especially if you use a simple and well-thought-out ISA.

I don't think many people honestly WANT to implement x86, because it's so difficult to do, and it is difficult to add cool features to, whereas RISC ISAs are usually rather simple to extend in many ways.

Just because an ISA is not created by Intel does nto make it modern (in fact, the x86 ISA is the LEAST modern ISA still in wide use).

Just a thought. (disclaimer: I'm not a computer engineer, and never will be. I'm a CS/Physics major, and I've taken one class in computer architecture)

Re:Amateur chip designers

[Anonymous Coward]

I did, but the facists at the FAA wouldn't let me fly it because they say egg cartons, popsickle sticks and tinfoil aren't 'flight worthy'.

Re:Amateur chip designers

[mrm677]

Take a few more advanced architecture classes.

ISA's are mostly irrelevant in terms of performance potential (except for IA-64 which I will get to). Both AMD and Intel devote a (small) portion of their transistor budget to dynamically convert the CISC instructions into RISC-like "micro-ops". Thus the actual execution core of the AMD K7 and Intel P6 micro-architectures are very similar to say the MIPS R10000 core. Now if Intel and AMD had a decent ISA to begin with, they could devote those transistors (used to convert CISC to RISC) to things like bigger caches. Thus the performance penalty of using a lousy ISA is really not that much as evident by the success of Intel and AMD in raw computational power.

Your comment about "RISC chips are really not all that complex" is extremely ignorant and uneducated. Please tell me again that the MIPS R12000 core is "not all that complex" after studying about superscaler speculative out-of-order execution.

The IA-64 ISA really is different because it takes a radical approach to achieving instruction-level parallelism. It is very VLIW-like and contains many advanced features like "poison bits", register windows (not SPARC windows), software pipeline support, etc. Thus the parallelism is discovered by the compiler and can be expressed to the architecture unlike RISC and CISC ISAs which rely on the hardware to discover and provide parallelism (through OOO execution).

Re:Amateur chip designers

[smasch]

Why can't an individual outsource too?

You can. Check out MOSIS. They will fab chips on one of several different fab lines for a reasonable price. For example, it cost about $8000 for 25 3mm by 3mm chips in 0.5 micron.

Re:Amateur chip designers

[PhoenxHwk]

It is infeasible for a new competitor to arise because of the capital involved

Rule #1 of an econ class I'm taking right now: capital is never a constraint for entering a market. It's out there; you just need to get it.

When the government is looking at antitrust cases, they get concerned when entry into a market isn't easy. And they don't consider capital an issue.

Re:Amateur chip designers

[Anonymous Coward]

Um, "college level" has very little to do with it.

Like most anything, modern CPUs are progressive improvment processes. 90% of what you need to know is gained on the job.

College supplies remarkably little vocational value. A BS equates to less than 1/2 year of full time exposure to general topics within the major. A MS is another 1/2 year, focused on a single specific topic. A PhD is another year, and focused on remarkably narrow topics. Full time college is, basically, a half time job.

In every case, a motiviated individual with both aptitude and passion can (and do) walk into university bookstores and procure all the info they need. Others engage in various projects, both free and in-corporate, that are far more difficult than ever expected of a MS candidate.

Anyone with an aptitude in the art will grossly outperform the average BS candidate within a year or two of workplace exposure.

So, anyone with passion enough to actively engage in such a project will also likely have the aptitude. They may enjoy reading a good university text, or two, and trying to apply that knowledge.

Re:Amateur chip designers

[Tazzy531]

The problem isn't really the amount of capital (you can get capital if you have a good business model). The problem is that there is a huge barrier for a new company to enter the market. I mean, just look at Transmeta. They were said to be able to take over Intel's position as the number one processor producers. Where are they now?

The main problem is that the industry has narrowed down to these two giants. They have brand recognition. I mean, if a CompUSA started selling PCs or Laptops with Transmeta chips next to a PC or laptop with a "Pentium" chip, which is the consumer going to pick?

Re:Amateur chip designers

[Tazzy531]

I can't think of an ARM implementation that is superscaler, speculative, and performs out-of-order execution.

But that's not the point. Not all processors were designed for general PC use. A good majority of the processors out there are embedded processors. The ARM/Thumb spec was designed specifically for this. It's other key feature is low power usage (which is very important for battery operated devices).

Re:Amateur chip designers

[kilrogg]

Then building the chip is another beast requiring a fab facility in the order of $1 billion for any process with feature sizes smaller than 0.5.

You don't need to build your own fab, there are fabs out there that will gladly build your IC for you, the most popular being TSMC. Many companies use external fabs (so called "fabless" semiconductor companies), including house hold names like Nvidia or ATI.

Mind you its still expensive as hell (0.25 ~ 1million US$ for your own mask set for an advanced process) which is why many amatures use FPGAs instead.

Re:Amateur chip designers

[Saeger]

Microprocessors are becoming so complex to design and build, that only a few companies are surviving.

7 posts preceding mine and yet no one has mentioned the inevitable solution to this [complexity] problem: evolution. There is just no way the human brain(s) can keep up, and at some point most design/engineering work will be done the emergent way... with much fewer humans specifying what to optimize for.
--

Re:Amateur chip designers

[johnnyb]

The question was on designing, not building. And yes, the design is the same question as building Linux.

Re:Amateur chip designers

[nelsonal]

There aren't too many traditional fab companies. AMD, Intel, Texas Insturments, Motorola, and SiS are the only ones that I know of that use their own fabs for most of their products. Some of the others do some foundry stuff and some internal stuff. Almost everyone else is strictly foundry. By the way the old Zilog fab in Nampa, Idaho is for sale. I would guess that $30-$40 million will get you a fully functional .35u process fab. You could offer them $25 million to start, if you were feeling cheap.

Re:Amateur chip designers

[Hast]

A lot of the problems involved in hardware design are logarithmically more diffucult than with software.

Concurrency tend to bite you? On a chip everything happens at the same time.

Is debugging a bitch? Try doing it with a hardware design where results happen concurrently and you have to run long simulations in order to even find potential bugs.

I've tried both, while software is a fun past time (At the level I do it.) I get head-aches from hardware design. ;-)

Re:Amateur chip designers

[Anonymous Coward]

>For a pure digital diesign you can then get away with a tool investment of $2-5000 for simulation.

What simulator are you referring to? If you're referring to a Synopsys or Cadence simulator then you're off by an order of magnitude. You might be able to get a copy of finsim from fintronics for this price, but even their list prices for their decent simulators are higher than this.

>For fabbing you should expect $20-50000 in expenses to ready your design for tape-out.

Again what tools are you referring to here? This seems off by at least a factor of two.

The numbers that you use in other places look more reasonable. For something like a 0.18 micron ASIC, the NRE that you pay to a very service oriented top-of-the-line Japanese company would be at least $500,000.

Re:Amateur chip designers

[WhaDaYaKnow]

There are only 2 remaining companies in this world that design and build 300+ passenger commercial aircraft (Boeing and Airbus)

Yeah, never mind the Russians. ;)

Re:Amateur chip designers

[Anonymous Coward]

It's totally possible for an individual to see immediate results. You can simulate a chip blueprint before you actually make the IC. Fab plants rely on this as their primary method of R&D. There's no other way around it.

So why can't there be an open-source processor initiative with blueprints and simulation results continually updated like software build numbers? Hey, why not?

Having said that, it's important to point out that software isn't just "soft" in name only. I mean honestly... does software performance actually follow anything REMOTELY close to Moore's standards? Software is soft... very soft.

I think the only new feature I've seen since Unix (invented 30 years ago) is the GUI (which is 20 years old).
Does anyone else notice the slow process that sotware goes through? If anything I'de say our software today is more bloated and slower than ever.

Compiler optimization may go up quickly... but only on the heels of the hardware. I don't see hordes of people donating time to open compiler efforts either.

Re:Amateur chip designers

[mrm677]

good point! guess i'm western-centric...

Re:Amateur chip designers

[Inthewire]

I agree. Are you hiring?

Re:Amateur chip designers

[svirre]

What simulator are you referring to? If you're referring to a Synopsys or Cadence simulator then you're off by an order of magnitude.

Modelsim PE can be had at around these costs (if you can negotiate well). Deepending on the market situation there may be emerging products that can be obtained cheaply. (A common tactic is to buy a cheap and crappy tool, then negotiate a deal with a vendor of a decent tool to switch in return for just paying maintenance)

2K is propably a too low estimate though

Again what tools are you referring to here? This seems off by at least a factor of two.

I was referring to the costs for paying somone else to do synthesis, P&R and tape out procedure. Not tools.

Re:Amateur chip designers

[Anonymous Coward]

Actually NEC just did that with their compact desktop "Mate" model...unfortunately so far only in Japan. Comes with a TM5800, thus needs no fan, is quieter and less powerhungry. I'd pick such a machine anytime.

Re:Amateur chip designers

[FrostedChaos]

I think you forgot the most important way of "getting into the 8-bit world":

You can buy a z80 for around a dollar.

(yes, I'm serious...)

Re:Amateur chip designers

[Anonymous Coward]

Great! Now I have a birthday gift for my son!

Sincerely,
William Gates
Founding Member and former CEO, Microsoft
"I LOVE this company!"

Re:Amateur chip designers

[Anonymous Coward]

Also, did you know that you have to go to medical school before you can become a medical doctor? I know it's hard to believe, but it's true.

Re:Amateur chip designers

[QuantumFTL]

ISA's are mostly irrelevant in terms of performance potential (except for IA-64 which I will get to). Both AMD and Intel devote a (small) portion of their transistor budget to dynamically convert the CISC instructions into RISC-like "micro-ops". Thus the actual execution core of the AMD K7 and Intel P6 micro-architectures are very similar to say the MIPS R10000 core. Now if Intel and AMD had a decent ISA to begin with, they could devote those transistors (used to convert CISC to RISC) to things like bigger caches. Thus the performance penalty of using a lousy ISA is really not that much as evident by the success of Intel and AMD in raw computational power.

I don't know about that one... I've read much about various architectures, even some about the IA-64 architecture (I'm rather excited about it, because a group of scientists here used it to achieve a threefold increase in their finite-element simulation performance using Itanium processors). I would say that having a lousy ISA constricts what compile-time optimisations can be done dramatically. Look at things such as compile-time branch prediction/prefetch instruction, predication bits, register rotation (granted that need not be part of the ISA, however to take full advantage of it, you have to know it's going to be there), speculative loads, cache hints, etc... You just can't do most of that stuff if your ISA doesn't support it! Implicit paralellism is often not good enough for intense applications. Also you must balance this against design issues with things like multiple instruction lengths, and worst of all about the x86- lack of registers! I'm quite aware that modern x86 implementations have many more internal registers, however that CANNOT POSSIBLY BE AS GOOD as having more visible, usable registers.

Often times, it's the compiler (or the programmer) that knows best, it sees the big picture. Having an ISA that doesn't allow you to define parallism, that doesn't allow you to save cycles in critical parts of loops, preload things, and makes you do a lot of unecessary branching, that CERTAINLY has a lot to do with performance. And lets not forget about SIMD instructions, or vector-based register operations (okay I know that hasn't been popular for a long time, but when you have a really slow processor it's actually rather attractive).

Your comment about "RISC chips are really not all that complex" is extremely ignorant and uneducated.

I actually meant to say that "RISC chips do not really need to be all that complex." If you don't do branch prediction, or register renaming/rotation, if you don't do multiple parallel instruction units, they are actually not that bad. I argue that a bunch of guys with bachelors degrees from a decent school CAN design something reasonably modern, just not as fancy and overly complex as an x86 CPU. I don't think the point of rolling your own CPU is to make something better than what you can buy for $100 at a computer show, but rather to make explore something that's quite explorable.

Also notice I didn't mention Itanium anywhere... that would be a nightmare, trying to design something even remotely similar. There's nothing too bad about doing explicit parallelism, in fact I would think that it's actually easier than implicit parallism, however some of the features they include are just wacky!

Then again, what do I know?

Re:Amateur chip designers

[sxpert]

This is already there...

The Free CPU project http://www.f-cpu.org has this purpose

Re:Amateur chip designers

[sxpert]

wrong assumption.
The fact is that there is a limited market for large commercial transports, as most planes are either flying (which does only cost the gas&pilots to the companies) and parked at the airport gate (that costs much more).
Thus there must exist only the number of gates + the number of possible flying planes + the ones undergoing checks, with the total number of planes having the proper capacity to fly every requesting passenger.
The only new planes required are replacements (with the old ones either being scrapped or stored in some desert).
Thus there is only a limited production of planes required.
Furthermore, the development of planes costing billions before seeing any returns, I enjoin you to start your own commercial plane building company and see in how many seconds you will sell your shirt off...

Re:Amateur chip designers

[Anonymous Coward]

True. But only if you go to a shitty school. Fortunately for me, most college students attend shitty schools.

Re:Amateur chip designers

[mrm677]

A lousy ISA absolutely limits the amount of compile-time optimizations with regards to parallelism. However RISC ISAs only make the compiler simpler as the instructions are more orthogonal and the register-coloring algorithms are easier. Compilers just aren't that good yet at discovering parallelism and can't express it with RISC either.

That's why register renaming and out-of-order execution was invented....to compensate for ISAs lack of primitives and the compilers inability to discover or express parallelism.

With register renaming, it doesn't matter how many logical registers there are. I believe the Intel P4 has over 40 internal registers. Combined with out-of-order execution, the machine dynamically determines data dependences and assigns a different logical register. It also dynamically determines which micro-op is ready to execute and does it. Having more visible registers often can make things slower. It creates unnecessary false dependencies that the hardware can't deal with. This is why the compiler technology is absolutely crucial for IA-64 which is, for the most part, a static execution engine.

Compile-time branch prediction is not such a great idea. You must profile the program which some fixed data set. With hardware branch prediction, the prediction tables dynamically adjust based on the execution of the program. Branch prediction combined with speculative execution is often just as good as predicated execution (i believe you are referring to this).

If you don't do branch prediction, parallel instruction units, multiple issue/retire, etc, etc...what do you have??? You have a slow processor certainly suitable for embedded applications bot not for modern general-purpose computing. Sure, rolling your own processor might be interesting to explore different computing paradigms such as SIMD. And it might make a cool hobby. But you have to ask yourself, will a 1.8 GHz Athlon do the job just as well as my 100MHz super-specialized-for-one-task processor??

And no, a bunch of guys with bachelors degrees and no experience can't build any decent general-purose processor. I'm not talking FPGA's because you can't use those to make a processor that is anywhere close to an Athlon. You need architects, logic designers, layout designers, packaging experts, fab experts, etc etc etc. Then there are so many subtle design issues such as precise exceptions, I/O, etc.

Re:Amateur chip designers

[SurfsUp]

The main problem is that the industry has narrowed down to these two giants. They have brand recognition. I mean, if a CompUSA started selling PCs or Laptops with Transmeta chips next to a PC or laptop with a "Pentium" chip, which is the consumer going to pick?

The one without the fan.

Re:Amateur chip designers

[QuantumFTL]

Compile-time branch prediction is not such a great idea. You must profile the program which some fixed data set. With hardware branch prediction, the prediction tables dynamically adjust based on the execution of the program. Branch prediction combined with speculative execution is often just as good as predicated execution (i believe you are referring to this).

Not necessarily, in fact many branches in programs are caused by loops (if you are looping from, say, 1 to 100, 99 times out of that 100 you WILL branch, and the compiler knows this). Also, if you use a language or language extension that lets you predict your own branches (versions of C++ do this, obviously assembly would do this), which, if you were in a tight loop you would probably want to do, then you'd be fine! And there's no reason you can't have an okay hardware branch prediction system that can be overridden by the program itself... simple branch prediction is very easy to implement in hardware, but it's not perfect.

If you don't do branch prediction, parallel instruction units, multiple issue/retire, etc, etc...what do you have??? You have a slow processor certainly suitable for embedded applications bot not for modern general-purpose computing.

Adding parallel instruction units is pretty trivial, scheduling them is not. But even if you can schedule them 50% efficiently (which is nowhere near as difficult as scheduling them 95% efficiently) and you can issue/retire multple instructions simultaneously, then you're still in the ball park, and in fact using a better ISA than x86, with things like predication, etc, could easily make up for some of that. Add to that that many many applications are limited by MEMORY SPEED and not processor speed, and you start to realize that your processor CAN be reasonably fast compared to an atholon with the same bus speed and io specs. In fact, putting the IO controller on your processor would shave a few cycles from your accesses, and wouldn't be super hard to do. Not only that, but there's no-one saying that you can't use nice standard external L3 caches to supplement your own.

And no, a bunch of guys with bachelors degrees and no experience can't build any decent general-purose processor. I'm not talking FPGA's because you can't use those to make a processor that is anywhere close to an Athlon. You need architects, logic designers, layout designers, packaging experts, fab experts, etc etc etc. Then there are so many subtle design issues such as precise exceptions, I/O, etc.

Not talking about FGPAs? That's what most of the artical was about, didn't you read it? I will definately agree that if you can't use FGPAs, it becomes a bit impractical (however students at the Rochester Institute of Technology, one of the places I applied for college, routinely cook up their own chips there, without being lpackaging experts or fab experts, etc...). That's not what the artical or the slashdot posting was really about anyways!

I don't think anyone seriously thinks they can do as well as hundreds of millions of dollars of development work, however doing reasonably good compared to them isn't really that impossible...

Re:Amateur chip designers

[rhost89]

Your kidding right, Have your programmed for the x86 CPU lately, with all the backwards compatibility crap i think a 4 year old could make a better processor whith these tools. Granted if they had to design the circutry on the die that would be a diferent story, but with these tools you just pick and choose the features you want.

Re:Amateur chip designers

[MountainLogic]

I believe that your are wrong in your basic assumption. The reason the big chip vendors have armies of Verilog sluggers is that they are trying to extend and optimize a static architecture with out taking advantage of significant possible performance advances in radical new designs. There is no way Intel is going to ship a design for the desktop that would not be x86 compatable. On the other hand, consider some radical designs such as:

256 very simple 8 bit CPUs on a chip

8K bit length instruction work CPUs

Both of these designs are within reach of current gate counts.

CS Lesson

[murat]

Every computer sciences (and engineering) major takes a course called something like "Microprocessors" or "Microcontrollers" and learns to design a microprocessor.

This course usually has prerequisite courses such as "Logic Design", "Computer Organization" or "Computer Architecture". Without those, it must be hard for non-cs guys to build a microprocessor. However, most of cool programmers/coders are not scientists, so it may also be possible.

Hackers in the garage?

[Anonymous Coward]

Hackers are evil criminals. We need to nuke the evil criminals!

Re:Hackers in the garage?

[bug5654]

Unless you are Bill Gates, Hackers are not evil criminals, just curious. The media makes the same mistake. Hackers are just good at what they do, but crackers are evil criminals. I must say that I'm surprised to see someone say this on /.

FPGAs

[zephc]

I attended an IEEE meeting at my school recently, and a guy from Xilinx presented and demoed FPGAs (their brand of course) and told us why we should use FPGAs for our signal processing needs. Of course, being an SE student, there were quite a few thngs that were over my head, but of course talking about the massive paralellism clicked with me, and of course hearing that one client of theirs had OC-768 signal processing within one FPGA chip, well, that was pretty damn cool. Also, being able to design your circuits with a nice GUI interface, rather than in VHDL or Verilog or whatever, looked pretty damn cool.

Re:FPGAs

[Anonymous Coward]

xilinx foundation is not the solution. it's a bug ridden pgoram if I evers saw one

Re:FPGAs

[svirre]

Right. You do _not_ want to deped on the supplied xilinx software for synthesis. It's pretty much crap. Use Synplicity or Leonardo Spectrum (to be replaced with Precicion synthesis this summer) instead.

Also, you do most definetly not want to design your circuit graphically. The time you are going to use to draw a single state machine graphically, I will have designed the whole circuit. Graphical design tools are OK for the structural design phase (this is however a miniscule part of the whole process), otherwise they ar pretty much toys. The best digital hardware design tool availible is Emacs.

Once you have learnt hardware design, and understood the difference between a programming language and a hardware description language, VHDL is quite easy to deal with (I don't know much verilog, and from what I have see I don't want to deal with it. It's a verification hell)

Re:FPGAs

[Anonymous Coward]

VHDL is old and shitty. Verilog is old and shitty. "The industry" needs a new standard HDL. State machines are for pussies.

Re:FPGAs

[svirre]

What's wrong with VHDL? What is it you want to express that you are unable to do clearly in VHDL?

And sure, you can design without explicitly making a state machine, but as long as you are making a synchronous circuit that is what it is going to end up as anyway.

While explicit state machines aren't right for everything, I have yet to see any sensible design methodology which can do away with them completely.

Re:FPGAs

[brejc8]

Well the thing is that I want to do asynchronous circuits which you actually have to use strange methods which are silly to describe in VHDL. The world is moving towards languages for needs. So asynchronous designers would use BALSA (asynchronous logic language). Im worning on a method of creating asynchronous circuits from synchronous descriptions like VHDL or schematic but at the end of it all it all gets mapped to a library of gates which is the much easyer to work with.

Re:FPGAs

[Anonymous Coward]

Sure you can express any reasonable clocked circuit using VHDL and Verilog but it is a pain in the ass and takes too long. There are plenty of better HDL alternatives out there but VHDL/Verilog is so dominant that nobody is willing to switch.

As for state machines, good luck designing a real CPU with them.

Re:FPGAs

[Izmunuti]

"The best digital hardware design tool availible is Emacs."

The verilog mode in Emacs is pretty nice. I like how it figures out sensitivity lists, port maps, and such for you. On the other hand I absolutely hate Emacs. I've never understood how anyone would actually want to use it, given a choice. I pretty much use Emacs in batch mode to auto-verilog files and I never have to look at it or hit ctrl-x, ctrl-c, or whatever the heck that 12-stroke sequence was.

No thanks...

[kentyman]

...I just took my Computer Architecture final last Wednesday. If I passed (by the grace of God) then I'm never thinking about MIPS again.

kentyman

/.ed allready

[Kizzle]

Since most articles are /.ed as soon as they are posted. I think a great feature for subscribers would be a mirror to each article that is hosted on slashdot.

Re:/.ed allready

[Thing 1]

Since most articles are /.ed as soon as they are posted. I think a great feature for subscribers would be a mirror to each article that is hosted on slashdot.

I'm currently working on Perl code to do just that. Haven't gotten very far yet, but the idea is automation -- write it once and let it mirror every article it sees.

If anyone else has already done this, or something like it, I could use the help. ;-)

To get back on-topic, perhaps we could burn that code into an FPGA so mirror update faster. (Yeah, right. You're gonna lose karma.)

Re:/.ed allready

[Thing 1]

(Moderators: I know this is off-topic to the story, but it is on-topic to the discussion. And to the site in general. And I'm posting with no +1 bonus. Thanks.)

Since most articles are /.ed as soon as they are posted. I think a great feature for subscribers would be a mirror to each article that is hosted on slashdot.

In a separate response to your post, I said I was working on Perl code to mirror stories' articles.

It's not complete yet; right now it grabs the /. page and splits it into stories, then splits each story into links. Then it prints each link.

The next part is to load each link (and images? What about multi-page articles?), and cache it somewhere. Then update the /. page, replacing each link mirrored with the mirrored location.

I know the lameness filter won't allow posting of code, so here is the script.

Point of FPGA processors

[brejc8]

The whole point of having an FPGA implementation is to allow you to get the latest version of the processor with a patch debug or improvement. Imagine compiling the latest distribution down to your processor and off you go. If you want it to do something special then hack the code.
www.opencores.org has many processors allready. I made a MIPS R3000 with a cache and MMU etc with minimal knowledge of hardware design.

Re:Point of FPGA processors

[Anonymous Coward]

no, you didn't make one. You put a copy of an original design that someone had clean-room'ed onto a blank chip.

Don't have to make the new Intel chip...

[fcrick]

I took a class in college where we learned how do this, with the last assignment ending with implementing a processor with 12 or so instructions.

The one thing I think I came away with is that you can built just about anything with FPGA's, whether you mean CPU's, or just controllers for large LED's, garage door openers, mp3 players or whatever...

There is a huge gap to fill in terms of geeks designing neat household or hobby chips that just do something that you need to implement in hardware (or firmware i guess). These devices don't need to be as fast as Intel or something, but there can certainly do something Intel's never done. I've always wondered why there aren't more open source projects built on this idea...any know? Anyone know where to look for these projects?

I guess a reality to recognize is that miniaturization (sp?) and faster processors with more features will eventually drive almost everything into the software arena (arguably already happened), so you might as well just write your cool device in and run it on your Linux iPaq or whatever replaces it...

Of course, I'm far from being an expert in this arena so this is just amatuer speculation...

Re:Don't allow whoever designed emacs to get ahold

[redhatbox]

Bah... RMS already has an Aibo pet that does all this and more...

In fact, it's mighty useful for voice activated control of the guided missile array on top of his fortified bunker compound with 18 inch thick steel garage doors driven by Emacs macros. I think the whole system's called "GNU/Fortress" or something.

This type of thing needs to be outlawed.

[Anonymous Coward]

Only properly government licensed and monitored programmers and technical people should be allowed to work on such technology as the potential for using this technology to violate the DMCA exists. Anyone who disagrees with this is a terrorist.

GOD BLESS AMERICA

Re:This type of thing needs to be outlawed.

[MoneyT]

OOOH IDEA! Use the processors you develop to circumvent the built in copy protection that the DMCA flunkies are trying to get put in VCRs, CD drives etc etc etc. Maybe even use em to rewire anyone who thinks the DMCA can only benifit society.

Re:This type of thing needs to be outlawed.

[Animats]

Use the processors you develop to circumvent the built in copy protection that the DMCA flunkies are trying to get put in VCRs, CD drives etc etc etc.

The scary thought is that the RIAA and the MPAA might try to outlaw private possession of FPGA design tools and burners for just that reason. If the "encrypted all the way to the monitor/speaker" concept ever takes hold, you'll need to build hardware to get unencrypted digital content out. And an FPGA is the only reasonable way to build one-off complex digital hardware.

Re:This type of thing needs to be outlawed.

[sxpert]

that has already been done with the copybit remover for sccs that was published in Elektor magazine about 3-4 years ago...

Re:This type of thing needs to be outlawed.

[sxpert]

it's called a connection on the speaker wires...

Re:This type of thing needs to be outlawed.

[cduffy]

Note the word "digital" content. If you connect after decrypt, it'll be analog (and thus lossy).

Companies take this stuff seriously.

[brejc8]

When I made my MIPS clone MIPS hot straight on my back sending me many threatening letters. Firstly they wanted to make sure I wasn't breaking any of their IPs. Then they wanted me to place a massive blurb to state I want anything to do with their company. Then they went down to the level of requesting my report of the building of this processor to use mips and a perfect adjective rather than a noun. Each time recommending that it would me much easier if I just gave up and took it off the web.

Re:Companies take this stuff seriously.

[Anonymous Coward]

Is English not your first language?

Re:Companies take this stuff seriously.

[brejc8]

That wasn't their point. They just didn't want MIPS to become another Hoover. People call vacuum cleaners hoovers and now hoover have lost their trade mark. Anyone can call their vaccum cleaner a hoover. MIPS are scared that calling a MIPS processor a MIPS (Microprocessor without interlocking pipeline stages) will invalidate their trademark. I had to grep through the report and replace each MIPS with MIPS microprocessor.

Re:Companies take this stuff seriously.

[Anonymous Coward]

No, I realize your point. I was wondering if English is not your first language. If you are learning it now, you are doing great.

I just did this!

[PenguiN42]

Ack! I just turned in my senior design project yesterday, after spending almost two all-nighters in a row getting everything to work. And guess what it was? A CPU designed from the ground up, implemented on a Xilinx XC4010E FPGA!

Course I did mine completely in schematic entry -- VHDL code is for wimps ;)

Re:I just did this!

[brejc8]

I open sourced my third year project which was made in schematics and I keep getting emails from people saying things like "I sound the schematics on your website but I cant find the VHDL source code".

Re:I just did this!

[Wyzard]

Actually it's the other way around: VHDL is better, and schematic entry is for wimps.

The reason is that what you draw in the graphic editor is not what actually gets put in the FPGA. I don't know much in detail about how FPGA's work internally, but basically, the compiler can look at a VHDL description and produce the most efficient gate-array implementation for it. Given a schematic design, it doesn't have a high-level sense of what the logic is supposed to do, so it's harder to produce an optimal FPGA implementation.

Your schematic design would be more efficient if it were implemented as you actually drew it, but not on an FPGA.

Re:I just did this!

[Bender_]

Schematic entry is for people who do not know VHDL. There is hardly any other reason to use schematic entry when doing CPLD or FPGA programming, because schematic entry does hardly give you more control over the PAR process.

Cleverly done VHDL can also give you close control over the actual logic. Just look at this CPU: 8 Bit CPU in CPLD. Even though it is done in VHDL it is optimized to fit just into the smallest CPLDs available.

Btw. I found above link on http://www.fpgacpu.org which is another good starting point for FPGA based cpus.

Re:I just did this!

[Anonymous Coward]

Wimps? Look at my FPGA wimp scale, you are pretty high up there:

*wimpier
VHDL Behavioral + Schematic Entry
Pure VHDL Behavioral
Schematic entry
VHDL Modular
VHDL Wire level
*kick yo a$$

Re:I just did this!

[lib]

"VHDL code is for wimps ;)"

...and for people who know its ALOT quicker to implement something in HDL's. Try doing something with a few hundred thousand gates in schematics & you'll see what I mean...

Just try doing this with 2 or 3 people in a month or two without HDL's:
http://www.eecs.umich.edu/courses/eecs470/ term_pro j.pdf

(Super-scalar (2-wide issue) Alpha ISA (64bit data path) processor, L1 caches, etc etc....)

Re:I just did this!

[Izmunuti]

"Course I did mine completely in schematic entry -- VHDL code is for wimps ;)"

Maybe so, but us wimps are getting a lot more sleep. Do you bang rocks together to start fires too? 8^)

I must admit that schematic entry does have a satisfying artsy-craftsy element that HDLs lack. But things are just getting too damn big these days to draw it all out.

Re:I just did this!

[Anonymous Coward]

Well, yes VHDL is for wimps..everyone KNOWS that Verilog is better!

It simulates faster, is easiser to read, and if coded properly, can give better QOR.

BTW: Schematic entry is nice, but try coding something in verilog gate level! I did it once for a VERY high speed circuit. (>400Mhz)..instantiated every wire, buffer, flip-flop etc..take that!

Re:Don't allow whoever designed emacs to get ahold

[hitzroth]

an open fortress? doesn't that defeat the purpose?

Hate to say it, but this won't fly...

[redhatbox]

NOTE TO MODERATORS: Yeah, this is off-topic, but comes up often enough that I thought I'd take a stab at it anyhow. Thanks.

This would probably make a lot of people angry. Your motives are great; you want the subscriber base of /. to enjoy the articles, without having to brutally flood some guy's server(s).

Trouble is, a lot of sites look to ad revenue to pay for at least some of the cost of hosting and bandwidth. If you mirror the article, most ad systems are "cut out of the equation." Now, this is sounding better and better for /. readers, but not so hot for the site operators' bottom lines. Even if the server goes down, the revenue from our traffic may be well worth the downtime (depending on the site, of course).

Maybe mirroring of academic articles (without ads or other profit-generation methods) would be appropriate, though. Or, maybe /. could try to contact a site owner prior to posting an article. Say, give the owner a couple of hours advance notice, and let the guy decide for himself if he'd rather be mirrored or /.'ed.

Just a few thought. :)

Re:Cheap Pars = Toasty Chips

[AlaskanUnderachiever]

OK. I help maintain a lab that is full of AMD's of various flavors. Now take a large heavy heat sink. Be a cheap ass admin and make sure everything is secured with inexpensive plastic bolts and cooled with cheap sleave bearing fans. Remember kids, even though these are going to get daily use from students and be suspended in an odd manner there's no reason to buy anything other than the cheap clips that came with the heat sinks. It's not terribly uncommon for someone to accidentally (yeah right) wack or move a machine with enough violence to weaken the clips holding the heatsink on. (ok I'm assuming that's what does it and we don't have an active army of super intel powered gremlins on premises). Heatsink slowly pulls away from CPU, eventually seperates one day, tada, rapid failure. Also the fans can fail. Either way, within a few minutes (or seconds if it's actually the heat sink and not just the fan) you have nice crispy chips. It doesn't happen very often, but take a lab of 40 computers x18 hours a day x freshmen and you've got a nice equation for failure.

Re:Don't allow whoever designed emacs to get ahold

[ActiveSX]

It's a Free fortress. Open fortresses are a different movement.

No, not quite....

[Colonel Panic]

Having done actual hardware designs (used to be a hardware engineer - now I've crossed over to the software side) targetting ASIC and FPGAs with both schematics and VHDL, I'd have to say that your facts aren't quite right.

In all probability when you use schematic capture these days (which is becoming rare) the schematic gets translated into what's called a 'structural' netlist which gets translated into either VHDL or Verilog and then passed on to your synthesis tool. Or, perhaps you get an EDIF netlist from your schematic capture tool and pass it to the synthesis tool (though most would probably be converting EDIF to something else).

Now, I can only agree with your point in so far as with schematics you do tend to have to instantiate every little gate in your design so you do (might) end up with sort of a hand optimized design (perhaps). However:
1) You can do this with VHDL or Verilog as well by writing your critical sections in a structural style.
2) With the current state of synthesis tools I would tend to trust them to do a better job of optimization than I can do.
3) You're not going to design anything sizable (like a real microprocessor) in a structural style or with schematics - it would take like forever and never get done. That's pretty much what we were doing back in the '80's - designs now are much to big to have to lay down individual gates.

The trend is always toward higher levels of abstraction (just like in software - we don't develop sizable pieces of software in assembler anymore). In fact, some of the newer C/C++ based hardware design methodologies seem to be pushing to even higher levels of abstraction than VHDL or Verilog (see: http://www.systemc.org )

(don't) Panic

Trademarks are adjectives

[yerricde]

Then they went down to the level of requesting my report of the building of this processor to use mips and a perfect adjective rather than a noun.

That's just common practice with trademarks. For instance, you'll never hear a commercial for the "Pentium" unless Pentium is followed by "processor". Further examples: SPAM is an adjective and should be followed with "luncheon meat." Java is an adjective and should be followed with "technology," "platform," or "language." Macintosh is an adjective and should be followed with "computer."

MIPS as a noun does not refer to a processor architecture. It refers to an easily-fudgeable benchmark.

FPGA Fun

[CajunArson]

OK, you can reimplement a modern processor core in an
FPGA if you really want to (I can guarentee you that
the FPGA will NEVER run anywhere near as fast as the
regular chip) or you can do what I did for our senior
design project

We used a Xilinx Spartan II to run the main board on a model helicopter control. The idea was that several sensors, including a 2 axis tilt, accelerometers, RF controller and an ultrasonic sonar could be easily integrated into the VHDL core, and then the chip would calculate 4 PWM outputs that drove the 4 motors. While the thing unfortunately didn't fly (weight problems, but hey, we're CompE's not aeros!) the board itself worked
great and the software UART outputted all sorts of fun data about what was going on.

Here's the interesting kicker: The entire system was clocked at a grand total of 1MHz (that's right folks, 1Mhz) and even that was too fast for most of the onboard operations that we internally clock divided. This thing operated all of the components completely in parallel, so there were no interrupts needed at all. The reconfigurability of the FPGA means you can quickly adapt it to solve a whole bunch of specialized problems very efficiently and quickly. This thing definitely met the criterion for a hard realtime system (motor updates within 1ms of a sensor or RF input) and it did it all
via VHDL code, no OS or any high level software needed.

Now obviously this is a very embedded solution and is not extremely flexible, but sometimes you need to step back and look at the true advantages that the hardware provides for you, and use it for something other than reimplementing someone else's CPU core, (of course, that
can be a hell of alot of fun too.... mmm... 21st Century overclocked Trash 80)

PS--> use my spam address: foxcm2000@hotmail.com and
I'll be more than happy to send you all the VHDL we used
to implement the project since I just graduated yesterday! :)

Re:FPGA Fun

[Anonymous Coward]

Congratulations! It sounds like a cool project.

Re:Don't allow whoever designed emacs to get ahold

[Anonymous Coward]

Linux isn't open because you don't have full control over the code (thanks GPL!). FreeBSD, on the other hand...

Already done...

[rbruels]

Our team designed a microprocessor on an FPGA for our final project in our digital logic design class.

It was a nightmare, to be honest, but ended up a sweet project. It had its own RAM, its own machine code, and a number of IO channels. The instruction set included arithmetic functions and branching instructions (compares, jumps, addresses)...

In any case, it was freakin' sweet. ;) And hell, I'm even a CS major... I actually found that yummy hardware goodness pretty fun.

Open Source Hardware

[Niscenus]

I had an article on this awhile back ago (toasted like AlaskanUnderachiever's previous four AMD's), but with the site now gone, I can't seem to find it in either google or wayback.

Anyhow, I think it is important that even hardware move over to the open source world. There are three requirements for this to kick off:

An inexpensive system for creating them

Knowledge and understanding of the standards involved

A central repository for updating and dissemination

If a common public utility for creating wafers could come out at fair cost (say, atleast equal to a computer, estimate $800 or so) that would be a major step for the first part. If the group involved at the IEEE for processor standards could freely distribute some or all of the necessary information, similar to as PARC did with POSIX, that would assist in the second. Finally, we would need a FreshMeat equivelant for hardware designs.

Processors are only a beginning...solid state technology, drives and cards would come fast thereafter. Is it an emerging field or something that will remain in the hands of the elite few who actually know the difference between a PSU and an FPU? I can wait you people out...I've been waiting out for the creation of massively distributed Open Source Software before many of you were born!

Re:Open Source Hardware

[Anonymous Coward]

Try OpenCollector for the hardware/EDA Freshmeat equivalent...

Re:Open Source Hardware

[sunspot55]

An inexpensive system for creating them

Good luck.. as a fab engineer I can attest that the last thing companies want to do is to make a die for every Joe Schmoe that comes along. The name of the game in fab is yield, yield, yield. As like a recipe for different cakes, each chip design has it's own recipe that must have the kinks worked out of. There is an enormous ammount of overhead going into starting a process and an enormous ammount of money going into improving the yield of a process. In short, the companies care about the bottom line, and unless people had millions to pony up for their custom designs it isn't going to be happening anytime soon. A company isn't going to let hundreds of millions of dollars of equipment run Joe Schmoe's home grown microprocessor when they could be churning out far more profitable Pentiums, etc. It's just like Boeing or Airbus, as someone mentioned earlier. Boeing can't afford to build a plane from scratch (ie VHDL) for everyone who had $800, it's just not feasible.

MMIX

[Merlin42]

So when can we expect to see actual MMIX hardware?

Re:MMIX

[Usquebaugh]

Oh please mod this up and pretend you have a clue :-)

Re:MMIX

[r6144]

I have spent several days writing a rudimentary MMIX operating system, and found that the processor has some flaws for operating systems, and the MMMIX simulator simulates some OS-oriented operations (like cache flushing) quite terribly. Therefore I think the design should get some improvement before it is ever hardware-ized.

Wonder if the link will work later?

[Anonymous Coward]

I notice that I get a "connection refused". Maybe that's what is known as slashdotting a site.

Anyhow, the link doesn't work right now. If anybody wanted to post a general rehash of the article here, I'd like to hear more about it. [Not quotations -- that might violate (C). But more about what these methods are, and what they cost to produce an actual chip -- that might be nice.]

[P.S. If anyone wants to tell the sysops, "Create Account" just takes you to the login page. So meanwhile sign me..."

Anonymous unable-to-register-clutz-but-not Coward.

Re:Cheap Pars = Toasty Chips

[CTho9305]

um... i've never seen an athlon die from fan failure. it takes a LONG time.

Senior Project

[jgomez]

I have been toying with the idea of making my own processor for my senior project. Of course, I can only do this in an architecture formant never be able to physically implement it. First, I tried it with a so-called "simpletron" with c++. Now with these new tools I could finish this project.

Wow.

[Anonymous Coward]

You are really lame.

Re:Wow.

[Anonymous Coward]

Shut up stallman, and give me back my dildo.

I'd rather imagine...

[The Monster]

just imagine a a cluster of these!

Instead, I'm imagining a chip that implemtents Java bytecode as its instruction set...

this is so much fun

[Edmund Blackadder]

I did this in college, (some 4 years ago). It was a lot of fun.

I designed a processor that had a stack for a register file. It worked like a charm. It was pretty serious design too with a pipeline of 4 or 5 stages and instruction forwarding etc.

It would have actually been usefull for an embedded processor that would be dedicated to run a stack based language, like Java.

Of course the next step is to design the whole thing on transistor level. And that is kind of a pain. Then you have to worry about having enough space to put everything etc, sizing all the transistors just right etc. Also you cant put that on FPGA, you have to be content with spice simulations.

But the gate level design is fun.

The site is down

[Anonymous Coward]

Muhahahaha...slashotted.
Aren't you scared of being charged of putting down sites one after another?

Java processor

[Anonymous Coward]

See the "links" page in the "Java Optimized Processor" site: http://www.jopdesign.com/

This ain't no fun

[drink85cent]

Wow now this takes the fun out of hacking out your own VDHL.

So now this is what it spits out right?

entity CPU is
port(a: in std_logic;
z : out std_logic);

end CPU

architecture struc of CPU is
component WEB_CHEAT
port(cheat_in: in std_logic;
cheat_out: out std_logic;
end component;

begin
entire_unit: WEB_CHEAT port map(a,z);
end architecture;

Another thought.

[_Knots]

A while ago /. ran a story (about a year after it was published, but that's fine) about a guy evolving software on FPGAs. That'd be cool enough, but the genetic algorithm figured out how to exploit *analog* and weak-linkage (adjacent gates crosstalking) aspects of the FPGA - so now not only do we have our own computers, we suddenly have our own combination analog/digital computers, should we want them, and it would be really cool to have an evolving computer... a genetic speech-recognition chip, or somesuch.

Just something I remembered.

-knots

stupidity plus luck

[sraak]

me neither, but i was very close.
i was building a computer. i put everything together, did some service pack installation, went to my room at my work, came back 4 mins later... something smelled... like after the thunder. i tried to move mouse, nothing happened. computer had "frozen" totally. i looked at the open case, noticed that fan+cloore where hanging with only one clip, and i rip the power cord away.

it was *kinda* fan failure, but the real reason was stupid user :-(

i forgot to plug the fan ps cable to MoBo! i grabbed the cable, got fancooler away. it was so hot i could not put my hand closer than 5 cm to it, something like over 100 degrees of celsius :-O
ok, i paid my learning money there, i thought, and our boss laughed friendly at me :-)

later i tried MoBo, CPU and memory, just for fun. and, hey ho, they worked! and the still do, CPU is at my firewall... at least it is officially tested real overclockers CPU.

strange, i thought it could never ever work...

FPGA CPU Resource: www.fpgacpu.org

[Jan]

See my company's FPGA CPU News site, and my three part (March-May 2000) Circuit Cellar series, Building a RISC CPU and a System-on-a-Chip in an FPGA and the accompanying XSOC/xr16 Kit, which includes schematic and Verilog versions of the processor, SoC, as well as C compiler (based upon lcc), assembler, simulator, specs, docs, test suites, demos, etc.

There's also an FPGA CPU mailing list, with almost 500 subscribers. Send mail to fpga-cpu-subscribe@yahoogroups.com to subscribe.

Many of us FPGA CPU hackers also frequent comp.arch.fpga on Usenet.

"I used to envy CPU designers, those lucky engineers with access to expensive tools and fabs. Now field-programmable gate arrays make custom processor and integrated system design accessible to everyone. These days I design my own systems-on-a-chip, and it's great fun."

You can too.

Jan Gray, Gray Research LLC

Back to the good old days

[nurb432]

When you actually had to understand the silicon if you wanted to compute...

Damned kids and their fancy pc's from the local market.. " i be elite " bah...

Reminds me of an old BYTE colum, where they built
a simple CPU out of descrete chips.. Such fun ( seriously )

Atari 2600 on a chip?

[Megane]

Anyone got the VHDL to a Stella-compatible video chip core? Add a 6502 core, and you've got 2/3 of an Atari 2600!

Re:Atari 2600 on a chip?

[Professor Nova]

Why a 2600? The chips used in the atari 8-bit
computers are in the public domain now.
So why a 2600-on-a-chip?
I want a 130XE-on-a-chip.

I disagree

[hendridm]

> Trouble is, a lot of sites look to ad revenue to pay for at least some of the cost of hosting and bandwidth.

First of all, this would be no different than what's in Google cache, which are often posted with Slashdot articles.

Second, if a site is Slashdotted, it has the maximum amount of viewers the site owners intended to visit at any given time, all exposed to their ads. Since they did not purchase the infrastructure to allow any more visitors to view their ads+content (by choice), it seems that they were not targetting anyone above that amount. So is it really a big deal if the rest of us see the content cached without ads?

testing

[lingqi]

I am kinda late in reply -- so no karma for me -- but for the record: i wonder how they test these suckers as they come off the toaster (haha, toaster)?

usually any chip would require a custom program to be run on a (very expensive, i might add) tester that will test the thing; writing the program is not cheap, i wonder how they factor in those costs? I wonder if anybody beside me on slashdot thought of this as a serious challenge?

Wrong sector

[Niscenus]

You seem to think that there was ever a chance in Redmond such a device would be made a major chip manufacturer. Such a thought is not unlike the idea that HP, Xerox or IBM was most likely to create a computer system for Mr. Schmoe. Behold, AMSTRAD, Commodore and the eventual Apple; the latter only being able to exist due to the irony in HP choosing not to chase the home market.

In this same fashion, I forsee a small, little known upstart, possibly started by the next Steve Wozniak, that, after playing with the idea, will try to see if there's a commercial place for it. The device will kick off in limited engineering/academia circles, much like the Apple, and then, a new type of company will be built, and with its rivarly, shall the others finally respond.

Re:Wrong sector

[sunspot55]

Only that if a company is going to *manufacture* Joe Schmoe's design, they'd better be pretty confident in it. Success in the fabrication field is measured in percentages of yield and volume. Small runs of every custom processor that come along are simply not economically feasible. That was my point, not that it's impossible for Joe Schmoe to come up with a good design, just that fab houses will *never* jump at the chance to manufacture every Joe Schmoe's design. There is a tremendous ammount of capital invested into the fabrication of a single chip design and I was commenting on the previous post's hope that there may be a market for cheap "quick turn" chip fabricators.

Re:Amateur chip designers-Deja Vu

[Anonymous Coward]

Yup! Use to be the senior project at ITT. The task would be broken up amongst the team. Each would be responsable for a particular section i.e. ALU, timing,cache,etc. That was fun. Of course thus was the era when tubes were the "thing" and the IBM PC could be understood in it's entirity.

AMD Had the technology once...

[lynmax]

AMD at one time had a bit-slice microprocessor, the 2900 and 29000 line, that allowed people to design their own instruction set. But that was back in the 80's and early 90's. It also involved a bunch of supporting logic to build a functioning system that required the use of a soldering gun to build a prototype.

Re:AMD Had the technology once...

[Adam J. Richter]

The 2900 series was a bunch of four bit wide components for building a processor, such as arithmetic logic unit and register file. You could arrange these four bit "slices" in parallel to build a processor of whatever bit width you wanted. A few components were later released in larger widths, to reduce component counts.

I believe that Three Rivers Computer in Pittsburgh, PA use Am2900 bit slice chips to build a successor the the Xerox Alto workstation. Carnegie-Mellon University had a bunch of these when I was in high school. The "PiRQ" (if I remember the spelling and capitalization) had a fourteen inch fixed hard disk, a portrait format bitmapped monochrome screen, a digitizer tablet, and a pretty slick looking enclosure.

The Am29000, on the other hand, was an urelated product that came much later. The Am29000 was the first mass produced single chip RISC processor. It was a 32 bit processor with separate busses for instructions and data, so that you could use dual ported memory or some other scheme to arrange for data accesses not to break the streaming of instructions.

I've been having a blast...

[graveyhead]

Just for kicks, I have been experimenting with my own processor design using TkGate for the past few weeks. TkGate is a great digital circuit simulator with lots of neat features.

I built a working lcd display simulator out of the built-in LED outputs that is connected to some video memory. I also built a data bus that is partially working. I am currently playing with connecting the ALU. I even built an assembler and a cheap assembly language for it :-) Once I add block device support, I want to write a simple OS with a built-in shell for it :-)

I did this as a CPE senior design project

[anonymous loser]

My partner and I design and implemented (on a large FPGA) a VLIW microprocessor. Our processor had 2 pipelines and a 16-bit registry.

The trouble is that you can't even come close to the number of pipelines or complexity required for a *real* modern processor using an FPGA. For example, in order to save space, we had to eliminate some of the more complex operations (e.g. divide & floating point instructions, on-chip cache management, etc.). And of course we were limited to only 2 pipelines, the minimum necessary to demonstrate parallel execution, which was kinda the point of our project. This was using the largest FPGA available at the time (250k gates, although there are bigger ones out now). Also, the clock speed of our processor was only 1-2 MHz depending upon how we tweaked it. FPGA designs are nowhere near what you could get with a design layed out and etched into silicon. A typical modern processor uses gate counts in the millions, easily 10-20 times what's available in a large FPGA.

While FPGAs are useful for simulation and experimentation, in the current day and age they just aren't fast and big enough to replace modern processors. If you're into making a small 8-bit RISC processor, or maybe implementing your own 6800 (or maybe a 6502 for you non-embedded folks) design, you can probably do pretty well, however.

Re:I did this as a CPE senior design project

[Space cowboy]

Hmm. I have a 32-bit processor, an i- & d-cache, an SDRAM controller, some h/w image processing, VGA output, and an audio/video interface on a single FPGA, using about 50% of a Spartan 300E.

I'm currently working on adding a JPEG enccoder and an ethernet MAC to the same, single, device. An S2300E has ~300k "marketing" gates on it, which isn't immensely larger than your own. Perhaps your design is more complex than my own.

The CPU runs at ~25MHz using just the synthesis tools PAR option set to max (takes about 10 mins to synthesize). I think I should be able to just about double that (I've had a similar CPU running at 48MHz on its own after applying a lot of RLOC's to the code).

The real advantage of this is that I don't have to have a computer - ultimately this will be a nice *small* device that will cost a lot less than even the cheapest PC + video capture + network card. An S2300E development board is only $140 from www.fpgacpu.com... I don't know how much the cjip itself is, but they must be factoring in *some* profit :-)

Simon

Re:I did this as a CPE senior design project

[anonymous loser]

I would guess my design is/was more complex. Is your proc a single pipelined RISC?

As soon as you add parallel execution, the amount of silicon required goes up dramatically. A 2-pipeline proc will take up much more than 2X the space of a single pipelined proc. Also keep in mind the 250k were "marketing" gates (effectively we had more like 180k-200k, of which a large portion were used for the writeback registy), and we also built a fairly advanced run-time debugger into the silicon as well.

It also sounds like there have been dramatic improvements in FPGAs since I did the project about 4 years ago, as one might expect given Moore's law.

OT: Re:Companies take this stuff seriously.

[RFC959]

They just didn't want MIPS to become another Hoover. People call vacuum cleaners hoovers and now hoover have lost their trade mark.

Discussions are so much more fun when you can just talk out of your ass, aren't they? From http://www.hoover.com/xq/asp/qx/docs/copyright.htm : "Some Of The Trademarks Of The Hoover Company: ...HOOVER®..."

So what was that you were saying about "hoover have lost their trade mark"? Your general point is correct, though - in the US legal system, you must aggressively defend your trademarks.

Re:OT: Re:Companies take this stuff seriously.

[brejc8]

From: http://www.cni.org/Hforums/cni-copyright/2002-01/0 063.html

"HOOVER is a US-registered trademark for floor-polishers,
carpet shampooers, vacuum cleaner BAGS, REPAIR of vacuum cleaners, lots of
other stuff ... but not for vacuum cleaners themselves."

Z80 based ZX81 in Spartan FPGA done.

[andrewmuck]

Yes folks a whole personal computer including the z80 core, have a look at zxgate.sourceforge.net

Misunderstanding

[Niscenus]

I'm not talking about a company that will produce designs that come in...I'm talking about a company that will produce at home systems to create them.

(hold for laughter)

I'm not saying it would necessarily be comparable to what chip manufacturers are capable of, but it is too early to say how it will develop. "Consider, if you will," the future means of development. Where was Ball Grid Array twenty years ago? Today, we have these large factory machines with huge arms with tiny miniscule "fingers" that carve and set those transistors onto wafers. But picture what happens at the very end of that tiny finger, and maybe it could be better than what you may expect...

Project the advancement of the field of the development, creation and deployment of nano-technology. Conceive of a device, a small box, about the size of desktop's UPS, like mine, the APC Smart-UPS 400: This device has a vacuum bay in the center with a transparent area over it, distilled water at the chamber's bottom, a series of small, barely visible sting-like lines forming a grid somewhere in the middle and a tiny arm on each side. When fed the information to the /dev/nwu (nanonic writing utility), those tiny arms start somewhere on the grid and coming from both between and outside of their "fingers" are little glimmering filaments that slowly weave into your processor.

Sure...it seems a long way off now, but with the rapid rate of technology today, I'll bet anything's possilbe tomorrow.

Re:Don't allow whoever designed emacs to get ahold

[Anonymous Coward]

Hold on there, cowboy! He didn't say it was open, he said it was free. Get some glasses, Troll.