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Typical Nvidia. Good point on the usefulness of FP16 in games and graphical applications as well. Now I'm regretting having gotten a (Pascal) 1070. This reddit comment says the AMD Vega and Nvidia Volta both have 12 TFLOPS single precision, but the Volta has 12 TFLOPS FP16 while the Vega has 25. Presumably Nvidia deliberately chose to execute FP16 calculations as FP32, because I'm sure they have FP16 support somewhere on die and their crappy driver or firmware cripples the card. I know what GPU manufacturer I won't buy from next time.

It would be even more interesting if RISC-V machines with vector units come out - that extension natively support FP16 (see the V-extension part of the user-mode spec on that site - right now, page 93, the part where they mention supporting a vector of 16 bit floats as a type), without having to go through a GPU driver or deal with nvidia and their ilk.

It should be noted that RISC-V also has a complicated decoder. "Compressed instructions" is just a soft way of saying it.

The complexity of the RVC decoder and the complexity of an x86-64 decoder are nowhere near the same.

The x86-64 can have instructions from anywhere from 1 to 15 bytes long, and it takes a lot of processing to determine how long an instruction is, especially with all the prefixes (like the REX prefix that sees so much use in 64 bit code for x86). This necessitates a state machine of some sort to parse the prefixes and apply their modification to the effect of the instruction in question. Each instruction is highly encoded, which requires a complex decoder to determine the length and operands, before the actual performance optimizations like register renaming begin. Additionally, each variable-length instruction may be split into multiple micro-ops. Intel makes highly performant processors despite, not because of, the instruction set.

Unless you have non-standard extensions, RISC-V instructions can either be 2 or 4 bytes (the 2 byte ones being the compressed instruction set). Instructions must be 2-byte aligned. It is trivial to calculate the length of any instruction in such a chip - if the least significant 2 bits are 11, it's a 4 byte instruction, otherwise it's a 2 byte instruction. In 4 byte instructions, the source and destination registers, and the highest bit of the signed immedate are always stored in the same place in the instruction word, allowing register renaming to execute in parallel, to a large extent, with actually decoding the opcode. The 2 byte instructions are not quite as clean, but still much simpler to decode than x86. (See page 70 of the RISC-V user-level ISA documentation.) Additionally, it seems that every 2 byte instruction is equivalent to executing a certain 4 byte instruction. (p. 81)

And yet, apparently RISC-V compressed is more concise than most variable-length encodings. (Including x86-64, IIRC. So much for "x86-64 uses memory bandwidth and cache more efficiently.")

Source for the RISC-V compressed instruction formats starts at page 67.

*sigh* it worked fine when i previewed it. https://groups.riscv.org/forum... - i've emailed help@slashdot.org they should fix it soon enough

i wanted to provide lots for people to debate, rather than just "repeat someone else's story" like much of the internet "news" tends to be these days.

A microcoded monstrosity isn't necessary to compete with CISC. RISC-V is a genuine RISC design, with a simple compressed encoding that bests both ARM and x86 on 32 and 64 bit code density, while also enabling high performance implementations with macro-op fusion. The minimal design and lack of condition codes also make it more friendly for Out of Order, and enable exceedingly good performance, area and power efficiency. (Beyond even ARM; see numbers in slides.) The entire instruction set and common extensions fit on a single slide.

See History of Computer Architecture and RISC (slides) by Dave Patterson.

Modern x86 chips are RISC processors, with an ugly compatibility layer on top which does have a cost. True, a number of processors that are ostensibly RISC (like ARM and PPC) do have many complex instructions and addressing modes, but the RISC ideal is alive and well with RISC-V. It is the best in class of conventional architecture, incorporating decades of wisdom. It offers a number of compelling advantages, and provides a solid and open foundation for future innovation.

There are a huge number of talks/slides available under workshop proceedings, for those with further interest.

See History of Computer Architecture and RISC (slides) by Dave Patterson.

Modern x86 chips are RISC processors, with an ugly compatibility layer on top which does have a cost. True, a number of processors that are ostensibly RISC (like ARM and PPC) do have many complex instructions and addressing modes, but the RISC ideal is alive and well with RISC-V. It is the best in class of conventional architecture, incorporating decades of wisdom. It offers a number of compelling advantages, and provides a solid and open foundation for future innovation.

There are a huge number of talks/slides available under workshop proceedings, for those with further interest.

See History of Computer Architecture and RISC (slides) by Dave Patterson.

Modern x86 chips are RISC processors, with an ugly compatibility layer on top which does have a cost. True, a number of processors that are ostensibly RISC (like ARM and PPC) do have many complex instructions and addressing modes, but the RISC ideal is alive and well with RISC-V. It is the best in class of conventional architecture, incorporating decades of wisdom. It offers a number of compelling advantages, and provides a solid and open foundation for future innovation.

There are a huge number of talks/slides available under workshop proceedings, for those with further interest.

See History of Computer Architecture and RISC (slides) by Dave Patterson.

Modern x86 chips are RISC processors, with an ugly compatibility layer on top which does have a cost. True, a number of processors that are ostensibly RISC (like ARM and PPC) do have many complex instructions and addressing modes, but the RISC ideal is alive and well with RISC-V. It is the best in class of conventional architecture, incorporating decades of wisdom. It offers a number of compelling advantages, and provides a solid and open foundation for future innovation.

There are a huge number of talks/slides available under workshop proceedings, for those with further interest.

The complete source code for the "Rocket Chip" core is on github: https://github.com/freechipsproject/rocket-chip. Other RISC-V cores are also available (see list here).

You can synthesize a RISC-V core right now and run it on a $99 FPGA board. Of course building an ASIC or fully custom chip is a much greater technical and financial (!!!) undertaking. That's the way the world works, and can't be blamed on RISC-V.

Uhh. This is not exactly new. The foundation has been around a few years and designs have already been made. Their easily identified website is https://riscv.org/.

So where are they? I mean this is open source right, and they aren't just throwing that around as a buzzword so where is the website for it, where are the specs, where is the 'how to' articles or anything else.

I don't know. Impossible to find anything.

https://riscv.org/

RISC V

Yes. There is already open source processor, called RISC-V:
https://riscv.org/

Yes, GCC and clang support generating RISC-V code.

Yes, GCC and clang support generating RISC-V code.

contain no [omitted] UEFI stuff

Minor nitpick: UEFI has been ported to RISC-V, but this CPU will most likely work with non-UEFI boot firmware.

How easy is it to keep working once abandoned though? Priorities change and companies get bought. The Broadcom SoC is proprietary, and the firmware and video are closed source blobs, making the system inherently untrustworthy. The ARM architecture itself is a proprietary mess, with no standard platform for an OS to target.

Before long, the proliferation of open hardware that can run standard OS distributions will tilt the scales, and provide an even greater guarantee of future support.

It is for this reason that RISC-V looks so attractive. Even with ARMv8, the spec is something like 8000 pages, and then there is the monstrosity of UEFI to deal with. The world desperately needs good open hardware with a standard platform, that is simple to both target and implement.

More interestingly, these are the guys behind RISC-V, the first royalty-free modern and forward-thinking ISA (instruction set architecture); the instruction set is designed to be modular, and it supports standardized implementations from this low-level kind of microcontroller all the way up to 128-bit (yes, that's right) general purpose or highly parallel computing.

It has a lot of industry support, and a commuting of very zealous tinkerers, who are working on all manner of open-source implementations of this open and royalty-free ISA.

RISC-V is a better option than POWER and there is substantial and growing support behind it. Good point about ARM by the way; people tend to forget that it is also proprietary since there is a competitive market build around it. However, ARM still maintains control and Softbank will be looking to squeeze more out of it. Open architectures provide a better foundation for innovation, allowing hardware to be composed in ways that are simply not possible today, or greatly complicated by licensing and other IP nonsense. Opening the architecture also enables participation and contributions by educational institutions.

The ARM platform mess is likely one of the reasons behind the rapidly growing support for the RISC-V architecture. The more obvious one being that no one wants to pay rent in perpetuity. ARM may not be as bad as intel, but they are definitely still a substantial burden on hardware developers, and a good open architecture and platform is what just about everyone wants. With Android being mostly platform neutral, I think ARM will also be in for a rude surprise, and turn out to have been a foolish investment for Softbank.

First of all, thanks for all of your amazing contributions to free software and free culture movements in general.

I would like to hear your opinion about projects to create free hardware, in particular CPUs like the OpenRISC and RISC-V, or projects striving to create full systems respecting the GPL and without binary blobs like Rhombus Tech's EOMA or lowrisc, or any other that you might know that goes beyond refurbishing existing computers.

In the case that you hold a favourable opinion, I also would like to know if the FSF is in touch (even informally) with any of the teams behind these projects and plan to support them in any way (other than accepting changes to GNU software so it can run in these systems), e.g. by working with them from early on to ensure that they can later be endorsed by Respects Your Freedom.

It's not clear what version of the MIPS ISA they're implementing (the article I read just said MIPS32, which covers a whole range of things). It sounds like it's MIPS32r6, which is not backwards compatible with any previous MIPS version. The only value of MIPS over something like RISC V (which is increasingly the standard ISA for computer architecture research) is that there's a large body of existing software for it, so you can do real evaluation.

We've done a clean-room reimplementation of MIPS III (R4K compatible) implementation in BlueSpec, which is a high-level HDL. MIPS III and the R4K are over 20 years old, so any architecture-specific patents will have expired. In comparison, this core is only 32-bit (really not interesting for research) and is written in a low-level HDL (making the kind of invasive changes that you want to do in research difficult), and is an ISA that has very little software support.

Also try riscv

If we have to change everything when upgrading from MIPS 32 bit to MIPS 64 bit anyway -- why not wait for (even contribute to) RISC-V -- instead of submitting to Imagination's burdensome license restrictions?

http://riscv.org/download.html#tab_qemu