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ARM's Own Employees Complain About Anti-RISCV Website (theregister.co.uk)

Posted by msmash on from the closer-look dept.

lkcl writes: Phoronix and The Register have an insightful look into an effort by ARM that is reminiscent of Microsoft's "Get The Facts" campaign. RISC-V's design is a revamp of the RISC concept that is intended from the ground up to fix the mistakes and learn from the lessons of the past 30 years. Power efficiency is 40% better than ARM or Intel. Compressed instructions reduce I-cache misses by 20-25%, which is roughly comparable to the same performance that would be achieved by doubling the Instruction Cache size. Yet despite El Reg's insightful analysis,
all is not as it seems: on further investigation, some of ARM's criticism has merit, whilst some of it is clear out-and-out FUD from ARM that, being so critically dependent on free software, had its own employees complain so much that the site was pulled.

Also we cannot help but wonder which "Big Chip" company offered seven-figure salaries to try to shut down the IIT Madras Shakti Project. Most interesting however is the fact that ARM -- a $40 billion dollar company -- is rattled by RISC-V enough to use underhanded tactics, whilst Intel on the other hand is actually investing.

89 comments

  1. Of course they are rattled by Anonymous Coward · · Score: 2, Interesting

    They reality is that there has been very little innovation in the area of computer architecture in the past couple of years.
    Only thing they have been doing is adding more cores.
    Once you have a completely open CPU design that fabs can freely fabricate as much as they want, it will eat up a huge slice of the embedded extremely low power market.

    1. Re:Of course they are rattled by 110010001000 · · Score: 0

      Exactly. Digital computing has hit a dead end, even though many Slashdotters hate to accept it, and it isn't looking good for the future. If they fix all the Meltdown/Spectre issues in the next generation it might cause that generation to be slower than the previous one. Eventually "open" processors will catch up.

    2. Re:Of course they are rattled by alvinrod · · Score: 5, Interesting

      I wouldn't say that. Companies like NVidia are doing a lot of work in designing cores that are made for deep learning and other types of specialty workflows where a general purpose CPU isn't as efficient or the amount of processing power needed is massive. Others like AMD have developed new interconnect technologies (they call it Infinity Fabric) that can be used to connect multiple small dies together on an interposer. This has massive ramifications as it means you can create massive dies in a much more cost-effective manner. We've also seen both Intel and AMD making moves towards APUs and with HBM (high bandwidth memory) it's eventually going to hit a point where x86 processors can become a SoC to that point that PCs become much more simplified. Maybe this doesn't have the wow-factor of some flashy new invention, but steady progress is often far more important than most of what people want to call "true" innovation.

      RISC-V is also an ISA (instruction set architecture) which is not an actual chip implementation. It's very similar to ARM in that it allows for companies to develop their own implementations of the chip, much like how Apple, Samsung, NVidia, and Qualcomm all make their own cores. The only difference is that RISC-V doesn't cost anything to license. You'll still need to pay chip designers to create an implementation if you don't have an open implementation that's free to use and there's no guarantee that any free implementation fits the use case that you'd want to target. Even if it does, there's still no guarantee that someone's proprietary implementation doesn't have such significantly better performance that it's better just to pay the additional cost anyway.

    3. Re:Of course they are rattled by 110010001000 · · Score: 1

      "deep learning" is BS. What they are calling "deep learning" cores are just compute cores with large programmable caches. Hardly innovative.

    4. Re:Of course they are rattled by bluefoxlucid · · Score: 2

      There are ANN hardware designs wherein computer memory cells are integrated with the circuitry of artificial neurons, such as an LSTM neuron. Rather than a bunch of RAM and some program code, there's a bunch of flip-flop circuitry (RAM) built right into the neuron circuitry to create a fully-functional neuron package, along with supporting circuitry to allow programming by wiring those neurons inputs and outputs to each other how you like and writing or reading their values.

      Theoretically, once you've programmed the contents and the connections, feeding input into the system would execute on-clock: if you have 5 layers of ANN, it should take 5 clock cycles to turn an input into an output. On a conventional CPU, you have to run a bunch of mathematical instructions which might take one cycle each, or be SIMD, or take multiple cycles for something like a division, or whatnot.

      MIT did some interesting stuff with that.

      --
      Support my political activism on Patreon.
    5. Re:Of course they are rattled by Anonymous Coward · · Score: 0

      Hmmmm, I seem to remember an open RISCV design that could be used by fabs as is at no cost. I can't seem to find a reference to it, so maybe I'm mistaken.
      And yes, advancements have been made in communication channels, but the actual processing parts have barely changed. For high performance this is important, but the market for low cost low power single core in embedded is huge, which is exactly where I would expect to see things like this taking over.

      Of course if I'm wrong about the open design existing (I could have sworn I read it less than a month ago) then yeah, it's less of an issue for them.

    6. Re:Of course they are rattled by Anonymous Coward · · Score: 0

      Maybe I should have specified that I was talking about GPP, not custom ASIC.

    7. Re:Of course they are rattled by Anonymous Coward · · Score: 1

      Yea...... neurons aren't binary flip-flops.

    8. Re:Of course they are rattled by Anonymous Coward · · Score: 1

      The next 10nm-based generation for Intel will have lower transistor performance than their refined 14nm++ and they freely admitted that (https://assets.pcmag.com/media/images/448825-10nm-technology-enhancements.jpg). If you have a Sky-/Kaby-/Coffee Lake the next ones are not going to be performance upgrades. And with the most recent Spectre-related issues (1.1 and 1.2) I don't expect any silicon fixes until at least Ice Lake in 2020.

    9. Re:Of course they are rattled by ShanghaiBill · · Score: 2

      In his Turing Award lecture, David Patterson made a similar point that there is a big potential for domain-specific ICs. Google's TPU is an obvious example, but there are many other examples.

    10. Re: Of course they are rattled by Anonymous Coward · · Score: 0

      The site wasn't even that negative on risc v, in fact, if these are the only attack points they found it is almost an advertisement against arm. It listed 5 points that everyone making chips knows and are not unique to risc v: design validation is expensive (this is for all socs, depending on complexity), you need to make glue logic around the core (same for arm, or your chip will be very basic), ...

    11. Re: Of course they are rattled by Anonymous Coward · · Score: 0

      The source code is available. You can run that through a place and route tool and get a very basic but manufacturable processor at almost no cost except production. A device like this is of course not competitive in the market but would be comparable to what you would get if you manufacture just the core arm licenses to you

    12. Re: Of course they are rattled by Anonymous Coward · · Score: 0

      Something like the iron triangle, but with 2 sides?

    13. Re: Of course they are rattled by Anonymous Coward · · Score: 0

      Found the AMD fanboi

  2. S my D by Anonymous Coward · · Score: 0

    woooooooo

  3. Intel by Anonymous Coward · · Score: 5, Insightful

    ARM is a technology company that makes all of it's money licensing it's IP. If people don't use ARM chips, they don't make money.

    Intel is a chip manufacturing company. They have their own CPUs, but they have also manufactured ARM CPUs (XScale) and licensed their IP for other chip manufacturers to use. I don't think Intel particularly cares what CPUs they make, as long as they make money.

    So, in the grand scheme of things, Intel probably wouldn't care about making RISC-V CPUs if they could make money doing so, whereas RISC-V is a direct threat to ARM's business model.

    1. Re:Intel by Rockoon · · Score: 2

      ARM's problem is that a good chunk of the big ticket ARM "established market" is mainly based on P-code/JIT technologies that are not specific to the ARM architecture. Changing the underlying architecture is mostly trivial. x86/x64 android runs the same stuff ARM android does, and so too will RISC-V.

      Without it being king of low power, why choose ARM?

      --
      "His name was James Damore."
    2. Re:Intel by Anonymous Coward · · Score: 0

      Intel abuses the x86 position massively. They certainly do care if you use something else.

      They just aren't completely dependent on it... unlike ARM.

      I mean, don't get me wrong. I like the fact that ARM really gave Intel a kicking in the low power space... but RISC-V can now give ARM a in kicking in turn.

      And RISC-V is better... and free... and we so badly need freedom down the chain in the hardware.

    3. Re:Intel by Logger · · Score: 3, Interesting

      I call hogwash on the claim that RISC-V is significantly more power efficient than ARM or Intel. I could not find the summary's claim of "Power efficiency is 40% better than ARM or Intel. " anywhere in the referenced material.

      I'm guessing he's misquoting this line "instruction cache access alone dissipated 40% of the energy in a five-stage RISC pipeline."
      Unless someone has come up with a RISC-V implementation that completely eliminates 100% of i-cache access power, in no way can you interpret that to mean RISC-V is 40% more power efficient than ARM or Intel. The paper does claim "[RISC- V compressed programs] fetch 25% fewer instruction bits than RISC- V programs", but that's comparing 2 different RISC-V ISAs; not RISC-V to ARM or Intel.

      I don't know enough about RISC-V to really say if it's ISA is inherently more or less power efficient than ARM or Intel. I'd be surprised if it wasn't better than Intel, and there's certainly room for improvement over ARM, but the only way to be that much better is *magic*.

      The real reason ARM is scared of RISC-V isn't some theoretical efficiency advantage that has never been proven out, but the free licensing structure. There's a lot of IOT designs out there that just need a good enough processor. There's also high volume embedded processor applications whose roadmaps don't don't foresee the need for continual processor improvements, so they'd rather not keep paying per CPU royalties to ARM when they don't care about future enhancements. In those markets cost is king, and it's hard to compete with free.

      Interestingly, the embedded markets I'm talking about don't use JIT. JIT based solutions require more memory, aka more cost. JIT based systems also have longer boot times, which is undesirable in these applications. Think, storage controller.

      The biggest JIT ARM users are actually in the smartphone space, and near term that space has other sticky reasons to stay with ARM. Compiler support ( really only the apps are JIT, everything else is C), debuggers, and lot's of other ARM IP that is bundled with the ARM license. That other ARM IP is not something most people outside of SoC ASIC design are familiar with. So giving up ARM is to give up a whole lot more than just the ARM processor, and isn't so easily replaced.

      I could imagine China encouraging Chinese companies to build a complete ecosystem around RISC-V, that could compete in the smartphone space though. That would align well with China's strategic goals, and probably scares the bejesus out of ARM. And if that is beginning to happen, I don't see how ARM could actually stop it. Really, they only can try to delay it.

    4. Re:Intel by religionofpeas · · Score: 1

      I've been programming ARM chips for the last 20 years, including on ARM-licensed cores on SoCs, and most of that time I have used the free GNU tools. Just like the RISC-V hardware is going to be good enough for most people, the same applies to free tools.

      Another consideration is that the ARM core that we had licensed for our SoC came with the restriction that we were not allowed to modify the source code. Only the external interface could be modified, not the core itself. Obviously, the RISC-V core doesn't have such restrictions, allowing users to implement their own, task-specific, modifications.

    5. Re:Intel by Megane · · Score: 1

      I don't know what color your glasses are, but the only "P-code/JIT technologies" that I'm aware of using ARM would be Android. And in that case, it would still take a lot of effort to port the whole system. The system is more than just the apps.

      There's a lot more to ARM's market than things that run a Linux kernel, such as the entire Cortex M line. And those already tend to be fragmented by vendor because even with the same core, each vendor has its own flavor of peripheral units. In these applications, C compilers are important, and almost never is binary compatibility important. In this market, ARM has competition with other architectures such as AVR, PIC, and MSP430, but with the technical superiority of being 32-bit. (Yes, I know about PIC32, which is really MIPS, the "other other" 32-bit architecture.) I'm sure ARM isn't too happy about another 32-bit competitor with an architecture that doesn't require a license to use its instruction set.

      So you're right, but for the wrong reason.

      --
      #naabhaprzrag, #sverubfr-000, #agi-fcbafberq, negvpyr[pynff*=' negvpyr-ary-'] { qvfcynl: abar !vzcbegnag; }
  4. This summary is a mess by wonkey_monkey · · Score: 4, Interesting

    I don't think I've ever read a more confusing summary. Clarifying that RISC-V isn't ARM's baby would have been a start. The subject of each sentence is also hard to decipher - is The Register's (do we have to call it "El Reg"? That's so twee) analysis about RISC-V, or about ARM's anti-RISC-V site? And so on.

    --
    systemd is Roko's Basilisk.
    1. Re:This summary is a mess by wonkey_monkey · · Score: 1

      Oh yeah, and you fucked up one of the links.

      --
      systemd is Roko's Basilisk.
    2. Re:This summary is a mess by Anonymous Coward · · Score: 1

      I don't think I've ever read a more confusing summary.

      So you missed Trump's take on the North Korea Summit?

    3. Re:This summary is a mess by 110010001000 · · Score: 0

      The submitter, lkcl, is one of the smartest people here.

    4. Re:This summary is a mess by Anonymous Coward · · Score: 0

      Slashdot isn't terribly good at explaining anything. The editors assumes everyone is familiar with every single technology. Like we're all supposed to know that RISC-V is some sort of Open Source instruction set, and ARM is a chip maker. Sadlly, it should take about 4-5 extra words just to clarify what this is about. This happens constantly as Slashdot has no idea what a resonable knowledge base is in IT.

    5. Re:This summary is a mess by lkcl · · Score: 2

      *sigh* it worked fine when i previewed it. https://groups.riscv.org/forum... - i've emailed help@slashdot.org they should fix it soon enough

      i wanted to provide lots for people to debate, rather than just "repeat someone else's story" like much of the internet "news" tends to be these days.

    6. Re:This summary is a mess by Anonymous Coward · · Score: 0

      This should not be upvoted.

      Summary could have been better, but the tone of this comment is unhelpful. Poster has a record of pointless negativity (calling things "twee" reeks of snobbery and add nothing to the discussion).

    7. Re:This summary is a mess by Anonymous Coward · · Score: 0

      Summary was fine if you have a basic understanding of what ARM and RISC-V is

      I thought this was a tech site, it shouldnt need explaining in baby terms for you. If its too complex for you to understand then do what normal people do: look it up

    8. Re:This summary is a mess by wonkey_monkey · · Score: 1

      That's a non-sequitur.

      --
      systemd is Roko's Basilisk.
    9. Re:This summary is a mess by wonkey_monkey · · Score: 1

      Oh, bugger off with the gatekeeping. Not everyone can be expected to know everything about everything. There's a reasonable level of explanation and this summary doesn't reach it. Should ARM need explaining to the Slashdot audience? No. Does RISC-V? Yes. It only takes a few words to lend the right amount of context.

      And all that aside, basic rules of clarity should apply. The editors shoud have edited it to a higher standard.

      --
      systemd is Roko's Basilisk.
    10. Re:This summary is a mess by Tailhook · · Score: 3, Informative

      I don't think I've ever read a more confusing summary.

      It might have helped if the first part of this had appeared on Slashdot. But yes, the summary, particular the title, is hopeless. A better title might be: "ARM beclowns itself with FUD against RISC-V"

      This is about ARM FUD against RISC-V that appeared yesterday on a new site setup by ARM marketing creeps. It was a shock to people that respect ARM, so much so that some argued it was a hoax. It took some investigation into the FUD site and its origins to convince people.

      The fact is that what ARM sells is being commoditized. It's being commoditized because what they sell isn't all that novel any longer. The core of an ARM based integrated circuit is a small fraction of the value of these devices today; they real value is in the peripherals.

      --
      Maw! Fire up the karma burner!
    11. Re:This summary is a mess by Desler · · Score: 1, Flamebait

      Ok. Since this is a tech site and according to your logic that means one should know everything about anything then please do the followinf:

      Write a fast SATD function in assembly using the Risc-V vector extensions and make sure to thoroughly document and explain each line with comments to how each line relates to the SATD formula.

      If you can't do this then kindly GTFO if you can't do something so basic.

    12. Re:This summary is a mess by Anonymous Coward · · Score: 1

      That says all you need to know about the average poster here.

    13. Re:This summary is a mess by Rockoon · · Score: 1

      People that comment every line are retarded.

      --
      "His name was James Damore."
    14. Re:This summary is a mess by Anonymous Coward · · Score: 0

      That's Luke for you ::grin::

    15. Re:This summary is a mess by datavirtue · · Score: 1

      Right. I thought it was a mad-lib until I read the comments.

      --
      I object to power without constructive purpose. --Spock
    16. Re:This summary is a mess by datavirtue · · Score: 1

      Not for machine code.

      --
      I object to power without constructive purpose. --Spock
    17. Re:This summary is a mess by Rockoon · · Score: 1

      yes, even for machine code

      stop being retarded

      --
      "His name was James Damore."
  5. Of course they are by pak9rabid · · Score: 0

    It's a free alternative that directly competes with them. See also: MS vs Linux

  6. I wonder why anyone cares at all by Anonymous Coward · · Score: 0

    I have been reliably informed by slashdot that architectural differences don't matter at all because of something called a translation layer.

    1. Re:I wonder why anyone cares at all by Anonymous Coward · · Score: 0

      Evidently not that reliably. Translation layers aren't free.

    2. Re:I wonder why anyone cares at all by Alwin+Henseler · · Score: 5, Informative

      I have been reliably informed by slashdot that architectural differences don't matter at all because of something called a translation layer.

      For modern, high performance cores like the latest x86's you may be right. With their billions of transistors, large multi-layer caches, out-of-order execution, pulling instructions apart into u-ops (and/or multitude of other tricks employed under the hood), some extra complexity in instruction decoding could be a minor part of the transistor budget. Changing little in terms of raw performance, power efficiency etc and making the CISC vs. RISC debate a moot point.

      But that's not what RISC-V is about. It's a clean-slate architecture.

      It's meant to scale. For a big high performance x86 a complex instruction set may not matter much, but if you're scaling down into low-power / low cost / embedded cpu's, a simpler ISA means smaller, cheaper, more power efficient devices. For scaling up, RISC-V provides for modular extensions to the instruction set. Making applications easy to move from low-end to higher-end parts (and vice versa). Or if you're into some many-core design, having a smaller / simpler core to start with, means you can put more of them on your slab of silicon.

      If virtualization is your thing, RISC-V architecture is designed from the start with that in mind. Not bolted onto a 20~30 year old architecture.

      Not to mention there's no IP royalties due should you want to bake your own IC's. For large-volume / thin-margin items, that could be a biggie even if you're talking a few $cents a pop (or thereabouts).

      Surely the above isn't all - check the RISC-V website if you haven't already. Given the number of organizations & companies behind, I think it's set to take over a large share in several markets. Probably in the long term though, from the low end up.

    3. Re:I wonder why anyone cares at all by Rockoon · · Score: 1

      But that's not what RISC-V is about. It's a clean-slate architecture.

      It should be noted that RISC-V also has a complicated decoder. "Compressed instructions" is just a soft way of saying it.

      The downfall of RISC was in part because is lacked a complicated enough decoder to allow a dense enough code stream to enable the instruction fetcher to pipeline multiple operations per cycle. The old limited pentium U and V pipes were enough to blow DEC's Alpha out of the water, let alone where x86/x64 is today retiring 4 or more operations per cycle on well optimized code.

      The RISC idea is an extreme end of the spectrum. x86/x64 is not the other extreme. In this case optimality isnt found at the extremes.

      --
      "His name was James Damore."
    4. Re:I wonder why anyone cares at all by Anonymous Coward · · Score: 5, Informative

      It should be noted that RISC-V also has a complicated decoder. "Compressed instructions" is just a soft way of saying it.

      The complexity of the RVC decoder and the complexity of an x86-64 decoder are nowhere near the same.

      The x86-64 can have instructions from anywhere from 1 to 15 bytes long, and it takes a lot of processing to determine how long an instruction is, especially with all the prefixes (like the REX prefix that sees so much use in 64 bit code for x86). This necessitates a state machine of some sort to parse the prefixes and apply their modification to the effect of the instruction in question. Each instruction is highly encoded, which requires a complex decoder to determine the length and operands, before the actual performance optimizations like register renaming begin. Additionally, each variable-length instruction may be split into multiple micro-ops. Intel makes highly performant processors despite, not because of, the instruction set.

      Unless you have non-standard extensions, RISC-V instructions can either be 2 or 4 bytes (the 2 byte ones being the compressed instruction set). Instructions must be 2-byte aligned. It is trivial to calculate the length of any instruction in such a chip - if the least significant 2 bits are 11, it's a 4 byte instruction, otherwise it's a 2 byte instruction. In 4 byte instructions, the source and destination registers, and the highest bit of the signed immedate are always stored in the same place in the instruction word, allowing register renaming to execute in parallel, to a large extent, with actually decoding the opcode. The 2 byte instructions are not quite as clean, but still much simpler to decode than x86. (See page 70 of the RISC-V user-level ISA documentation.) Additionally, it seems that every 2 byte instruction is equivalent to executing a certain 4 byte instruction. (p. 81)

      And yet, apparently RISC-V compressed is more concise than most variable-length encodings. (Including x86-64, IIRC. So much for "x86-64 uses memory bandwidth and cache more efficiently.")

      Source for the RISC-V compressed instruction formats starts at page 67.

    5. Re:I wonder why anyone cares at all by AmiMoJo · · Score: 1

      RISC-V will probably never have performance even approaching x86. There is a lot to like about it, but you won't be seeing it used for high performance applications like games consoles or workstation CPUs.

      The main reason is that the RISC concept itself turned out to offer much less flexibility for making optimizations on the CPU. A modern x86 CPU treats the x86 instructions as a kind of intermediate language that it dynamically translates into microcode operations on the fly, doing massive optimization in terms of concurrency and access to slow/contended resources like RAM.

      With a RISC CPU the idea was to remove a lot of the opportunities for that kind of optimization, the belief being that such optimizations would be too complex for CPUs to do anyway and that the simpler architecture would scale better to higher clock speeds.

      RISC-V does support out of order execution, but it's no-where near the complexity of what modern x86 does and the scope to reach that level just isn't there. On the other hand it's great for when you need energy efficiency or reduced complexity.

      --
      const int one = 65536; (Silvermoon, Texture.cs)
      SJW, n: "Someone I don't like, and by the way I'm a fuckwit" - AC
  7. My Thoughts by DaMattster · · Score: 4, Interesting

    ARM is scared of losing it's death grip over IoT and smartphones. Usually active FUD campaigns bely this real concern. One day ARM will have to come to grips with the fact that it will be toppled. ARM is about to repeat the same expensive mistakes that Microsoft did with its Get The Facts campaign.

  8. Of course Intel is investing by Anonymous Coward · · Score: 2, Interesting

    All this time they've been living from the x86 architecture. Their last significant architecture change was Sandybridge, concocted in Israel rather than Intel headquarters. Now they have Spectre and Meltdown and AMD is running circles around them with Ryzen. They killed off Alpha by hooking HP on Itanium and then killing off Itanium. MIPS died from a culture of binary distribution/compatibility (simulating non-interlocking 3-stage pipelines with half-interlocking 7-stage pipelines is just absurd). ARM is not exactly new. Everybody is moving to the cloud and tablets and app stores where putting up new ecosystems on different architectures is comparatively easy and Microsoft is running Windows proper into a corner where everybody wants alternatives.

    If there is any time for changing horses, it is now.

  9. come at me hoe by Anonymous Coward · · Score: 0

    the red fox trots quietly at midnight.

  10. Please work on literacy by Anonymous Coward · · Score: 0

    Please attempt to develop English language abilities expected of a high school freshman before trying to be cute with things like "El Reg."

    Really. This is absurd.

    1. Re:Please work on literacy by lkcl · · Score: 1

      Please attempt to develop English language abilities expected of a high school freshman before trying to be cute with things like "El Reg."

      Really. This is absurd.

      it's what they call themselves! and i lurnd inglish from bwainiac https://google.com/search?q=br..."i+can+do+science"

      https://en.wikipedia.org/wiki/...
      https://google.com/search?q="el+reg"

  11. Kiss my piss!! by Anonymous Coward · · Score: 0

    A stable genius? *snicker*

  12. 7 figure salary... by Anonymous Coward · · Score: 0

    Hey guys, this is probably in rupees. So, 5-6 figure salary in dollars.

    Still, hats off to the guy for turning down a large pay hike.

    1. Re:7 figure salary... by lkcl · · Score: 1

      Hey guys, this is probably in rupees. So, 5-6 figure salary in dollars.

      Still, hats off to the guy for turning down a large pay hike.

      i couldn't put it in the main article, but i spoke to Madhu back in november, and it was USD $24 million. i still won't say who the company was but you can guess easily. and yes, turning down that much money is extremely brave. basically he realised that he could either be another PhD in amongst 100 other PhDs, or he could go back to his country and help his citizens reclaim sovereignty over their computing devices. when you're faced with that kind of decision it's not really a choice that you can walk away from with a clear conscience.

    2. Re:7 figure salary... by jkuznech · · Score: 1

      i couldn't put it in the main article, but i spoke to Madhu back in november, and it was USD $24 million.

      Luke that number is preposterous. Brian Krzanich never even received that much. Also it is a little misleading to characterize GS. Madhusudan as "another PhD in amongst 100 other PhDs". He is the one of the leaders of India's homegrown semiconductor movement.

    3. Re:7 figure salary... by lkcl · · Score: 1

      i couldn't put it in the main article, but i spoke to Madhu back in november, and it was USD $24 million.

      Luke that number is preposterous.

      then that gives you some idea of how much of a threat A... err... the unnamed company that tried to bribe^Whire their engineers.

      Brian Krzanich never even received that much.

      Also it is a little misleading to characterize GS. Madhusudan as "another PhD in amongst 100 other PhDs". He is the one of the leaders of India's homegrown semiconductor movement.

      my understanding was that it was neel who received the "offer", but i can't be sure. ahh.... yes it was. ohhh that's reeeallly interesting. fuckers who published the article REMOVED the bit about neel's "offer"... and "the author of the article no longer works with us". mmmm rrriiiight....

      https://web.archive.org/web/20...

      "Some of that open source zeal can be seen in the Shakti team here. Gala, who was offered a ‘good seven digit package’ by one of the big chip giants, decided against it. “This was an interview over a cup of coffee. The moment of realisation for me was sitting in the cafeteria, and seeing a hundred other PhDs there. The only distinction I had over them was Shakti. If I left it, I would just be another ball in the bag. So that’s why I didn’t leave,” he says."

  13. Power of techies. by d.w.mitchell.55 · · Score: 1

    It must be awesome to be so good in your field that you get to call out your own companies FUD, without getting fired or blacklisted. I don't know if tech people will ever figure out how powerful their technology has made them.

  14. Re: The thing about Trump, prison is made for him by Anonymous Coward · · Score: 0

    So your telling him to make his posts great again? lol

  15. Sources for RISC-V speculation? by jkuznech · · Score: 1

    Luke could you provide sources for your claim that "some of ARM's criticism has merit?". The link provided is to your own mailing list post. I have been following RISC-V closely, and I'm curious what the "systemic failures" you describe there are.

    1. Re:Sources for RISC-V speculation? by lkcl · · Score: 1

      Luke could you provide sources for your claim that "some of ARM's criticism has merit?". The link provided is to your own mailing list post. I have been following RISC-V closely, and I'm curious what the "systemic failures" you describe there are.

      *sigh* that's difficult to do, to provide "independent" sources, as no fucker is brave enough to put their neck on the line and stand up to them. the only reason i can publicly hold them accountable is because:

      (a) i'm used to challenging people (and getting banned and censored and then predictably 100% so far seeing the project fail or fork or undergo a major change in leadership within 6-18 months)
      (b) i'm not affiiated with a university, so do not have a "tenure" that could be threatened
      (c) i do not work for a company, so there is no employer to fire me (and no shareholders or profits to think of, first)
      (d) i am not even a member of a software libre project so have no "standing" or reputation to be destroyed or have my team members ostracised

      so... pretty lonely if i'm honest!

      over the years i've read enough to be able to watch for the signs, and to give people the opportunity to sort things out for themselves... if they so wish. the six Systemic Laws of Organisations listed in "Invisible Dynamics" is one of the best guides i know. any one of those Systemic Laws gets violated, an organisation is guaranteed to be in trouble. *fixable* trouble... if they choose, but still trouble nonetheless. what's interesting about those Laws is that one of them is "denial". including denial of the existence of the Six Systemic Laws!

      Bob Podolski's "Bill of Ethics" is the benchmark against which i.... how can i put it... self-check my own behaviour / decisions. the BoE includes a mandatory requirement to always seek (and accept) constructive feedback.

      for the Libre RISC-V project however things have to be a little different. this SoC is important. what i used to do is: let people kick me out (basically). if they wanted to be self-obsessed narcissic lying bullying motherfuckers i gave them every opportunity to be otherwise, but never, not once, backed down. the subsequent fall-out that was witnessed (and archived permanently for everyone to see) had the desired effect... but here i can't let that happen.

      so in this case i'm trying a different approach, using this page http://www.crnhq.org/12-Skills... as a literal step-by-step guide to resolving issues. one of them interestingly is called "Appropriate Assertiveness", which is the main "skill" i am having to apply right now. it's specifically listed as "not nice" and as "a necessary first step" in a resolution process.

      so far, sadly, however i have yet to actually receive a response from anyone where i have had to use that guide. there does not appear to be *any* interest from the key founders behind the RISC-V Foundation in actually acknowledging that there's a problem (Systemic Law violation, "Denial"), and i can guarantee that's going to bite them, sooner rather than later.

      this despite trying to warn them that the Shakti Foundation is backed by UNLIMITED resources from the Indian Government, and if the RISC-V Foundation doesn't get their act together they'll fork the entire RISC-V software and hardware eco-system, and over the next 5-10 years drop a hundred million completely incompatible processors onto the planet, causing *exactly* the scenario that ARM described in their now-offline website.

      it's not crunch-time yet, but it's close.

    2. Re:Sources for RISC-V speculation? by jkuznech · · Score: 1

      (b) i'm not affiiated with a university, so do not have a "tenure" that could be threatened

      I believe the purpose of tenure is to grant academic freedom to the researcher. I don't see how criticizing RISC-V would "threaten" a tenured position.

      over the years i've read enough to be able to watch for the signs, and to give people the opportunity to sort things out for themselves... if they so wish. the six Systemic Laws of Organisations listed in "Invisible Dynamics" is one of the best guides i know. any one of those Systemic Laws gets violated, an organisation is guaranteed to be in trouble. *fixable* trouble... if they choose, but still trouble nonetheless.

      Do you know of any online reference to these "systemic laws?" If these laws are reasonable, I'd like to perform my own analysis of the RISC-V community's stability. If there aren't any references online, would you mind briefly outlining what the six laws are?

      this despite trying to warn them that the Shakti Foundation is backed by UNLIMITED resources from the Indian Government, and if the RISC-V Foundation doesn't get their act together they'll fork the entire RISC-V software and hardware eco-system, and over the next 5-10 years drop a hundred million completely incompatible processors onto the planet, causing *exactly* the scenario that ARM described in their now-offline website.

      Hmmm, this does seem like a worst-case scenario, but I don't see any incentive for the Indian developers to pursue a hard fork, especially if they are planning to release RISC-V commercial processors. A hard-fork for the governmental sector seems more plausible, but that would hardly jeapordize the integrity of RISC-V.

    3. Re:Sources for RISC-V speculation? by lkcl · · Score: 1

      (b) i'm not affiiated with a university, so do not have a "tenure" that could be threatened

      I believe the purpose of tenure is to grant academic freedom to the researcher. I don't see how criticizing RISC-V would "threaten" a tenured position.

      whilst i am well-known (even myself) for not known for getting things totally accurate, i'm sure you know what i mean: a student or professor publicly criticising a highly-respected person... for example david patterson to pick one hypothetical name, would raise... a lot of eyebrows.

      over the years i've read enough to be able to watch for the signs, and to give people the opportunity to sort things out for themselves... if they so wish. the six Systemic Laws of Organisations listed in "Invisible Dynamics" is one of the best guides i know. any one of those Systemic Laws gets violated, an organisation is guaranteed to be in trouble. *fixable* trouble... if they choose, but still trouble nonetheless.

      Do you know of any online reference to these "systemic laws?" If these laws are reasonable, I'd like to perform my own analysis of the RISC-V community's stability. If there aren't any references online, would you mind briefly outlining what the six laws are?

      the book's available on amazon, my copy's in storage and i really wish it wasn't. it costs quite a lot to replace https://www.amazon.co.uk/Invis...

      as i can best recall them they are listed on page 23 with their associated "anti-laws" if that makes any sense, and they are something like:

      * all contributions by all members, past and present, shall be respected.
      * both the length of service and the level of expertise of any member shall be respected and taken into account
      * there shall be no "denial". acceptance of "what is" is crucial.

      i'm really sorry but those are the only three out of six that i can recall vividly. they're pretty obvious, and you can almost certainly think of situations in which you've seen these Systemic Laws be disregarded. hilariously a lot of them are the subject of Dilbert strips. CEOs telling you that "everything's well" (when it clearly isn't) has an *extremely* damaging effect as it completely locks up the *entire* company.

      this despite trying to warn them that the Shakti Foundation is backed by UNLIMITED resources from the Indian Government, and if the RISC-V Foundation doesn't get their act together they'll fork the entire RISC-V software and hardware eco-system, and over the next 5-10 years drop a hundred million completely incompatible processors onto the planet, causing *exactly* the scenario that ARM described in their now-offline website.

      Hmmm, this does seem like a worst-case scenario, but I don't see any incentive for the Indian developers to pursue a hard fork, especially if they are planning to release RISC-V commercial processors. A hard-fork for the governmental sector seems more plausible, but that would hardly jeapordize the integrity of RISC-V.

      it does if i am helping them to create a mobile-class processor, that goes into smartphones, tablets, netbooks and chromebooks, which, due to their reduced cost due to huge volume, result in them being sold out of india on amazon, making their way world-wide, and people find that they're not DRM-locked and that they can quite easily replace the OS right down to the bedrock.

      the problem will come when they find that the standard debian-riscv and standard fedora-riscv distros.... don't work. they'll then start investigating and find that they need a complete total hard forked version of debian, fedora and so on. at that point it becomes hell for the debian and fedora maintainers, who are pretty much guaranteed to be swamped with requests for support of such low-cost low-power hardware.

    4. Re:Sources for RISC-V speculation? by jkuznech · · Score: 1

      whilst i am well-known (even myself) for not known for getting things totally accurate, i'm sure you know what i mean: a student or professor publicly criticising a highly-respected person... for example david patterson to pick one hypothetical name, would raise... a lot of eyebrows.

      Isn't this a general criticism of any democratic system? It would raise a lot of eyebrows because one would expect that the authority figure is qualified in making his/her judgements. I'm still not sure what the issue is here.

      hilariously a lot of them are the subject of Dilbert strips. CEOs telling you that "everything's well" (when it clearly isn't) has an *extremely* damaging effect as it completely locks up the *entire* company.

      "Don't be Dilbert" seems to be a good mantra to follow.

      it does if i am helping them to create a mobile-class processor, that goes into smartphones, tablets, netbooks and chromebooks, which, due to their reduced cost due to huge volume, result in them being sold out of india on amazon, making their way world-wide, and people find that they're not DRM-locked and that they can quite easily replace the OS right down to the bedrock.

      the problem will come when they find that the standard debian-riscv and standard fedora-riscv distros.... don't work. they'll then start investigating and find that they need a complete total hard forked version of debian, fedora and so on. at that point it becomes hell for the debian and fedora maintainers, who are pretty much guaranteed to be swamped with requests for support of such low-cost low-power hardware.

      What is the motivation for the Shakti engineers to deviate so far from the base ISA that their hardware will no longer be compatible with the general ecosystem? Also, I still don't understand how any of these criticisms are due to the management of the RISC-V community. This just seems like a general criticism of any open-source/libre project. I apologize if I'm sounding too defensive of the RISC-V community. To now, I've believed that RISC-V is being competently led and managed. I really do like to see a future where RISC-V is the Linux of ISAs, and your alarmist comments are troubling me.

    5. Re:Sources for RISC-V speculation? by lkcl · · Score: 1

      whilst i am well-known (even myself) for not known for getting things totally accurate, i'm sure you know what i mean: a student or professor publicly criticising a highly-respected person... for example david patterson to pick one hypothetical name, would raise... a lot of eyebrows.

      Isn't this a general criticism of any democratic system? It would raise a lot of eyebrows because one would expect that the authority figure is qualified in making his/her judgements.

      eeexactlyyyy. and unfortunately, we are talking about people who, by virtue of being professors, are used to teaching, used to being always right, and used *never* to being questioned. and, indeed, *in their area of expertise*, they are almost 100% right, 100% of the time. this is an example of the systemic law "respect expertise, respect length-of-service".

      unfortunately there are two (quite different but related areas) where this becomes a problem:

      (1) when the experienced and long-standing expert encounters something OUTSIDE of their area of expertise and
      (2) when there exists confusion between SPECIFICATION and IMPLEMENTATION ADVICE (implementation-specific optimisations)

      the first should be fairly clear: someone who is used to always being right, suddenly has to deal with someone who knows more than them. this is happening particularly in the embedded field: liviu and many others who have a lot more experience in the embedded world, and who have implemented embedded cores for a living, are finding it *REALLY* difficult to deal with the experts in the RISC-V Foundation. and even MIT had to fight tooth and nail to get a simple one-page specification chapter added, so that they could explore a different type of (more secure, formally-provable) memory-model.

      the second is a different variation on that: people who *do* have similar domain expertise to the experts within the RISC-V Foundation are finding that the specification has many many areas where a decision has been made on the basis which basically boils down to "well nobody in their right mind would ever want to do this differently because in OUR experience and to OUR knowledge, that's sub-optimal, therefore we can optimise out all and any possibility of ALLOWING anyone to do different from what WE DICTATE, by actually TELLING people in the specification, it MUST be done this way and this way alone".

      there are dozens of examples where this has happened, and unfortunately, the amount of effort required to do anything different, due to a cascade of critical dependencies, is quite literally man-decades of work and millions of dollars worth of ostracism from "The One True Way".

      i'm being deliberately harsh, there, so as to emphasise the extent of the problem.

      in terms of the Systemic Laws, we're basically seeing a clash between people with similar levels of high *non-overlapping* levels of expertise, but where the founders clearly have the "length of service".

      "Don't be Dilbert" seems to be a good mantra to follow.

      basically... yes. :) but you know how Dilbert is disregarded by Management :) whereas something that's been used regularly and successfully for 20+ years by extremely large companies like Mercedes Benz and contains neutral rational advice is much more likely to be taken seriously.

      What is the motivation for the Shakti engineers to deviate so far from the base ISA that their hardware will no longer be compatible with the general ecosystem?
      Also, I still don't understand how any of these criticisms are due to the management of the RISC-V community. This just seems like a general criticism of any open-source/libre project.

      first thing, the RISC-V Project is *not* an open-source / libre project. it's Trademarked, and the Trademark takes absolute precedence. secondly, it's a restricted (closed) group, you have to sign the RISC-V Member Agreement just to gain acc

  16. What were they thinking? by Alioth · · Score: 1

    What where they even thinking to launch a smear site like that? It's certain to backfire: the message such a site gives is that RISC-V is a serious challenger to ARM, if ARM has to go out and smear it, and people who've never even heard of RISC-V will now be checking it out because this kind of story gets picked up by the computing press and gives a huge amount of free publicity to RISC-V.

    --
    Oolite: Elite-like game. For Mac, Linux and Windows
  17. Re:No computing in Federal Prison by datavirtue · · Score: 1

    Nor is this the place to respond to trolls.

    --
    I object to power without constructive purpose. --Spock
  18. Re:No complaining about websites in Federal Prison by datavirtue · · Score: 1

    Of all the buffoonary implicit to Trump his election most likely staved off a war with Russia. Most people have no idea how heated and sensitive the rhetoric had become, a lot of which was showing up in the election. Both the Democrats and Republicans were railing against Russia while the behind-the-scenes diplomatic situation deteriorated. It was as if they were trying to back Russia into a corner to prompt an action.

    The US was pressuring Russia, pushing Putin's buttons, while exclaiming to the American public how evil and militant Russia is. All because they want Russia to back out of Crimea and Ukraine. Both the US and Russia are trying to influence the self-determination of the eastern European countries along with the EU.

    --
    I object to power without constructive purpose. --Spock
  19. Much ado about nothing by Waccoon · · Score: 1

    Am I the only one who actually read the archived web site and figured their talking points were pretty benign and reasonable? I mean, RISC-V isn't even a full spec at the moment and is still a work in progress.

    Like most things I've come across in the open-source world, RISC-V is a bunch of good ideas, but ARM has proven, working implementations of their own ISA. From a business perspective, it's not outlandish to boast about that. If ARM were tearing apart the concepts behind RISC-V, then that would be a different story.

    As The Register's analysis wasn't actually very thorough, let alone insightful, I'd suggest looking at the original criticism before letting loose the nerdrage.