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Mamba: Athlon And DRAM Get Together
scottnews writes: "Tom's Hardware has posted this story about a new chipset for the AMD Athlon processor with 8MB of embedded DRAM in the chipset for 9.6 GB/s of sustainable bandwidth." Thatsa spicy meatball.
Micron actually does an excellent job of building chipsets. They bought a company that did motherboard work for exactly this reason (I can't remember who, but it was someone who specialized in high end stuff). The Samurai chipset was the result of this, and it was one of the early adopters of 64-bit PCI. Indeed, this would have been THE high-performance chipset if Intel hadn't come out with AGP at the same time.
Trust me, these guys are very good at what they do.
sigs are a waste of space
My Handspring Visor has 8Mb of RAM and cost about $250. My 1983 computer had a 10Mb hard drive and cost $4000. My current home computer has 256Mb of RAM and cost about $1300. My 1992 computer had a 220Mb hard drive and cost about $3000.
I like this trend. I expect to see a computer with gigabytes of ram on my desk in a few years.
The next Cmdr Taco duplicate will be ready soon, but subscribers can beat the rush and see it early!
I hope they do well, and I hope this come to realization. I also hope that VIA and AMD can produce better chipsets (like the AMD760), so that there are no more drawbacks to using a great CPU.
--
"How many six year olds does it take to design software?"
dinner: it's what's for beer
It is pretty common for large regular structures like cache's to have a little extra that can be used if some of the memory is bad. I don't know if that is the case here, but it may be. It is also possiable that they can just map out part of it (so there might be a 7M version).
Even if so it will cost extra. There is extra time on the tester, and tester time isn't cheap. Also if it is better (or though to be better) there will be more buyers which can result in a higher price...or in research and devlopment intensave products lower prices, so who knows :-)
I'm sure it took longer to design as well. So the 8M of RAM isn't free, but it should be a lot cheaper then it normally would be, or at least more profitable to them.
I like how Taco decides he needs to bypass any load balancing software Tom's Hardware might have and link DIRECTLY to a server in the farm. :)
> I think Intel is doing just fine. Why? Name recognition. It's as simple as that.
However, the longer the current situation persists, the more erosion into name recognition Intel will suffer. Arguably, that is costing them more than the lost sales.
--
Give me a candidate who speaks out against the war on drugs.
Sheesh, evil *and* a jerk. -- Jade
> Intel suits must be laughing their arses off as they hand AMD the "enthusiast" crowd
But as we said, that status quo is eroding every day so long as Intel sits on their fat arses and lets AMD get further ahead in performance (and further behind in recall rate). Businesses are dumb, but lots of them catch on eventually. Lots of those enthusiasts are also sysadmins.
If Intel lets it go too long, there is likely to be a catastrophic "landslide" shift in business's buying habits.
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Give me a candidate who speaks out against the war on drugs.
Sheesh, evil *and* a jerk. -- Jade
With the high pad count on what's essentially a dataswitch, your core will easily be pad-limited (Note however that modern bonding techniques can get considerably more pads in on a die than before)
That said; it isn't free to utilize extra 'filler' silicon on the die, as this will lower yield as defects that prevously didn't drigger a fault since it was on whitespace, now causes a defective unit.
Micron also asserted that the added cost for the eCache is minimal - "virtually free" are the words Micron's Dean Klein used.
Ordinary Athlon - $600
Athlon with Mamba(TM) - $850
Cutting edge technology, now matter how "free", tends to overly inflate prices. 'Twould be nice if it didn't though.
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you may quote me
Really neat idea.
;)
L3 cache integrated into the chipset. Except it doesn't really COST anything, because it's only taking up what used to be wasted space!
And in the process they cut L3 latencies (off the norm anyway) by 50% and are sending back to the CPU hella bandwidth.
I like.
I want.
Give! Sorry, tech widthdrawl...I'll get over it in an hour or two
You've got bandwidth going to/from the processor. You've also got the extra bandwidth going to/from main from the L3 cache memory. Then you've got the bandwidth going to/from the southbridge, agp bus which I'd be willing to bet they're have pass through the L3 cache...
It's still more bandwidth than required, but more of it can be used than you think.
The fact that it is an L3 isn't the cool part.
As you said, the fact that it's on the chipset is cool as hell. However, there are additional advantages to putting it on the chipset over traditional L3 caches. Lower latencies and higherbandwidth are the big ones.
Why do we have so much bandwidth in the L1 and L2 cache? Because if you have data in it, hitting it, things are much MUCH faster than hitting main memory.
Just because the memory talks to the chipset at 100 or 133mhz doesn't mean that the chipset talks to the cpu at that speed. In fact, that's one of the things that makes the EV6 bus design so flippin cool. The chipset on the K7 talks to the CPU at an effective 200 or 266mhz. Lots of bandwidth.
Erm, this isn't an AMD design.
;).
This is a chipset created by Micron. You know, the guys who are really good at making embedded SDRAM. There was a big noise about it about a year or two ago before it fell off the charts. Looks like they did something usefull with it this time
So when you get right down to it, AMD can only gain from this. They can't loose, because they're not the ones making it.
Oh I guarantee you that they notice it's not being used. The question they probably ask themselves is
"can we make this any smaller or rearrange it to use space better?"
"Nope, sucks don't it."
"Yeah."
The Micron guys didn't try to do that. They thought "what else can we fit in there" *evil grin*
The OP (evanbd ) said: "The FSB can't sustain it anyway.", so you're kind of missing the mark, there IMO. Do the calculation: at 200 MHz effective clockrate, a 128-bit wide bus can transmit 2.98 GB/s. And IIRC, the EV6 bus isn't 128 bits wide, but only 64. That's not even a third of the bandwidth handled by this memory controller, so it does seem a bit too hefty. For one processor, that is... I never understood if the Mamba chipset is for SMP or not. If it is, then things look differently.
main(O){10<putchar(4^--O?77-(15&5128 >>4*O):10)&&main(2+O);}
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Nicotine free Amish .sig.
Disclaimer: this is a "I heard from a 'reliable source'"-type rumour.
<rumour>
That said, a good friend of mine worked at Intel c.1998 as an intern. He states that Intel at the time lost money on every Celery they sold. How does the processor division stay profitable? The Xeon processors. If this was indeed the case (he didn't work for the finance area, he worked as a geek there), and if it still is the case, then Intel suits must be laughing their arses off as they hand AMD the "enthusiast" crowd, and they take the server arena. Most businesses I know still won't trust AMD with their servers, so even the current crop of 2-way-only Xeons (which are probably just regular PIII's mated to the slot-2 package) can recoup the losses in the consumer arena.
</rumour>
That said, the Athlons seem to be great processors (though I've never used one--the newest box here is a Mobile PII-366 =P)). Maybe that's why AMD is so keen on getting in on the server market?
Just looking at the books of both AMD and Intel can be rather revealing; in The Register's words, AMD is still a chimp compared to Intel's 800lb gorilla.
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Still good for AMD, as this is a chipset designed to support the AMD Athlons. Yeah, it's a Micron chipset, but AMD has said repeatedly in the past that they're not in the chipset business. Of course, after the 760MP chipset announcement, I tend to take that with a bit of salt.
Then again, this may be a killer uniprocessor chipset, but I would've loved to see a 4+way MP chipset with specs otherwise similar to this, taking full-advantage of the EV6-protocol that the Athlon uses.
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The specs look pretty good too The AMD 760 MP chipset is a DDR SDRAM solution that can support two 266MHz FSB Athlons. The chipset has advanced buffering to enable maximum transaction concurrency
"Science is about ego as much as it is about discovery and truth " - I said it, so sue me.
I expect to see a computer with gigabytes of ram on my desk in a few years.
What?!? In a few years? How about today?
We are buying 1GHz Thunderbird machines with 1GB of SDRAM for $2500 ea. And that's in a rackmount chassis. Put it in a regular desktop case and use the savings to get an AGP video card and LVD SCSI hard disk.
Screw Micro$oft.
This is the link to the main server and this wan DOES work #)
good for them. With the recent troubles that Intel has been having, I wonder how long AMD is oing to be able to keep up the pace without a stumble. More power is always good, but is quality suffering?
Dirty Pirate Hooker
Heh. They "noticed" that 40% of the die space was unused?
ENGINEER BOB: Hey Steve, I just noticed that we're only using 60% of the die space on the Samurai.
ENGINEER STEVE: Hmm.... Damned if you're not right! How did that slip past us in the months we spent designing it? Good thing you're on the job, Bob!
-- He's fantastic, made of plastic....
umm, DEC Alpha mobos have had 8MB of L3 for quite a while, and K6-3's had integrated L2, which made the on-mobo cache L3... Of course, no one's put it in the chipset directly before, so that part's cool as hell. But L3 cache itself is old news.
If violence isn't solving your problems, you're not using enough of it. - MAJ Misato Katsuragi
All I can think right now is that I'm glad that I don't own stock in Intel.
What is Intel going to come out with to top an Athlon at 1.5ghz (and that's with AMD's current core)...
A P4 with a whopping one pound heatsink and that requires a new power supply?
You know, I won't buy one, if I can buy an Athlon that I may even be able to keep my A7V for. (And for a few hundred dollars less, as well.)
The FSB can't sustain it anyway... so why 9.6GB? I can understand the lower latencies, those will be useful, but that bandwidth??? even FSB and IO together can't.