Intel Creates 30-Nanometer Transistors
SirFlakey writes: "It appears Moore's law has been proven right yet again. According to a report in Fairfax's IT section, Intel has managed to create the world's smallest transistor(s). This, according to the article would allow them to create CPU's with 10 times (420 million) the P4's transistor count. The transistors are only 3 Atoms thick(!). They say they have come close to the limit of modern technology but also still have plenty of innovation left for the future. This annoucement comes only a few days after it released an earnings warning for this quarter."
Good point. So perhaps IBM can etch silicon wafers down to such lilliputian dimensions, but what about thermal instability? With 3-atom-wide transistors, I'm guessing the number of electrons needed to hold a charge in a flop ain't all that much, and the alpha radiation from nearby lead (e.g. solder) could become a big(ger) concern.
Or did they forget to mention such a device is really only reliable around absolute zero?
Aid for the clueless: smaller transistors put off less heat so you can run them faster. Smaller transistors can be packed more closely so you can run them faster. Smaller transistors can have more of them fitted to the same chip, allowing nifty architectures so you can run things faster.
In other words, smaller = faster.
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The lattice constant (distance between the center of adjacent atoms) in silicon is 5.43 angstroms. Thus one would assuem that 30nm (300 angstroms) is actually about 55 atoms thick.
Most likely the 30nm refers to the gate length and the 3 atom reference was a 'misguided' measure of the gate dielectric thickness. The reason I say misguided is because dielectrics tend to be molecules not atoms. Although 3 molecules is thin, such thicknesses have already been reported before.
So much spin. But I guess it makes sense since IEDM (International Electron Device Meeting) is occurring soon and everyone loves to get excited about the newest small transistors.
It expects to sell 400 million-transistor processors able to do 400 million calculations in the time it takes to blink.
Thanks for telling us the calculcations per blink, that's a real useful measurement system.
The inverse proportion even runs to metaphors. I remember an ad or article or something a few years ago about how this speed-demon new CPU stole the poor engineer's coffee break -- well, now he'll get it back while the damn thing reboots. Maybe with a vacation thrown in for lagniappe.
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They'd just skip trying to go smaller and move directly into phase 15: Creating talking llamas whose entire cell structure is a computer.
Kinda gives whole new meaning to GIGO and WYSIWYG, eh?
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Every major advance in the last 40 years has been due to increases in clock speed and switch density. Cute tricks like caching and dual-piping or whatever they're calling it this year are flea bites on the butt of real progress. Remember what an "advance" the 486 was over the 386? The corporate boojums need things to market so they make things up when there's nothing real in the pipe, but when something real comes along it doesn't have to be marketed to you because you sure as damn hell notice it.
I mean, my relatively nonobsolte PIII is real cool, but would it really be that much cooler than a machine with 486-level architecture running at the same 450 MHz? For that matter I have to wonder how my tired old 8-bit friends would fare if one could run them at a good fraction of a GHz. Sure, you buy some extra clocks with all those extra transistors trying to second-guess look-ahead your code, but I wonder if that's the best use of all that high-speed silicon. Maybe a *cough* beowulf cluster */cough* of, say, Z80-level CPUs all fabbed on one chip and running at 1GHz could do some really interesting things by comparison.
If this thing is real then great for Intel and for us, it doesn't really matter what architecture they apply it to; and if it isn't real it won't save them when something that is does come along, not matter how good their press releases are.
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I was just talking with a collegue working on Bose-Einstein condensations (BEC) and I asked what some of the uses were. Due to the way BECs work statically/quantum mechanically one can create any interferance pattern within the BEC. He said that there are people working on trying to figure out ways of using this property to replace the etching processes used today to create things like computer chips by creating a interferance pattern in the form that one wants and then laying the BEC on the matterial (there is more to it than that but you know that). This would allow for manufacture of things at the 3 atom level. Of course, as someone else mentioned, 30 Nanometers is larger than 3 atoms thick. Lattice structures of silicides are roughly between .1 and .9 nm [1].
Theoretically this is possible, now whether this is practical is a whole different ball park.
[1]V.E. Borisenko: Semi-conducting Silicides (Springer, New York): pp 3-5
Disclamer - Opinion of Person
Actually, we don't use the same thing that was invented in 1947 for ICs now. There are all kinds of transistors. BJTs, IGBTs, FETs, MOSFETs. The latter being the type used in modern semiconductor technology. Forgive any errors (I've not yet taken solid state), but whereas a conventional transistor emits a collector-emitter current proportional (the gain) to the base-emitter current, a MOSFET's gate is a capacitor (in fact the capacitors used for DRAM are just MOSFETs) where the current through them is proportional to the voltage across the gate. They are much more disposed to on-off operation than operation over a linear region, because it requires minimal (gate capacitor leakage current) energy to maintain a MOSFET gate state, whereas to represent a '1' on a BJT would take a constant supply of current, irregardless of whether it had changed recently or not.
BJT = Bipolar Junction Transistor
IGBT = Insulated Gate Bipolar Transistor
FET = Field Effect Transistor
MOSFET = Metal Oxide Semiconductor Field Effect Transistor
As you can see, there have been many advances more significant than having the boys in the back room develop a better/smaller/faster/more powerful widget.
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What I can't see is how one can lay down anything 3 atoms thick (or wide) reliably (in the sense of real-world mass manufacture, not one of a time in-the-lab productions) using scaled versions of existing Fab tachnologies and without some nano-assembler type technology. Worst case you'll get 3 atoms somewhere in the middle of the wafer and maybe 5 or 0 at the edges ....
This sort of tech will come one day - but I beleive it's going have to be by revolution, not evolution ....