New Photolithography Process

dragons_flight writes "Motorola has announced a new photolithography process capable of making chip features smaller than 100 nm, with the aim of eventually going as low as 13 nm. For reference, the current next-generation standard is 157 nm."

Comments

Features != transistors....

[wowbagger]

Being able to make "features" as small as 13 um (and remember, "as small as" means this is a lower limit, and includes all sizes larger than this, up to Ringworld and beyond....) does not translate into working transistors at this size. You start getting into quantum tunnelling through the gate oxide because it is too thin, you start getting into a very high on resistance because the channel is too thin, the interconnects start to electro-migrate at 1 volt, etc.

Making small features is only a very small part of making a working chip.

Is there a semiconductor physicist in the house?

[Anonymous Coward]

I would be interested to know just how much current you can push down a 13nm-wide metal track without overheating it. That parameter would (partially) determine the voltage at which you could run such a chip, right?

Then, assuming that transistors scale down nicely by two orders of magnitude from the current state of the art, how much voltage do you need to bias them? Even on today's 1.8V ICs, you're looking at a gate-drain voltage of 0.6V -ish. Is this compatible with the requirement to reduce the operating voltage to avoid heat death?

Etching really small things into silicon... good work, but I think there are many major engineering challenges to overcome before they can say "we've got a 0.001 micron process, ner ner ner ner ner". I shudder to imagine how many times they're going to have to revise their SCMOS design rules between now and then.

Why do I get the feeling I'm spoiling this for everyone else? :-)