Intel Chips For The Near- And Semi-Near Future
Brian writes "This
article reports that Intel will release new chips at the Comdex
trade show, its first low-power designs for super-thin servers. The
new Pentium III model is a
gussied-up chip taken from the company's product line for portable computers,
which share many of the same constraints as ultradense
servers. These systems can't consume as much power or give off as much heat as
ordinary CPUs because overheating causes processing errors. The systems
are the first swing of a one-two punch against Transmeta,
whose low-power designs caught Intel
flat-footed, first in the mobile market and then in the low-power server market. Intel now is fighting back just when most
server companies using Transmeta chips
are on the ropes." And albat0r writes: "Intel says that it will hit 3GHz on the mainstream Pentium 4 by the end of 2002. Intel will advance its Celeron line, currently based on Pentium III technology, with Pentium 4 technology by mid-2002." I look forward to good values on eBay when 2GHz is "obsolete."
Interestingly, I've just read a review of the first system (to my knowledge) that uses the nForce board as it's core. It's from Mesh and was reviewed in the December issue of Personal Computer World in the UK. The review slateted it quite badly, saying that it's 3D performance was down even on Budget versions of the GeForce 2 card on which the gfx engine on the board is based. Mesh also seemed not to have bothered wiring up the cool onboard sound system the nForce carries. My advice : Wait a while folks - the first nForce systems are going to take a while to run really swish!
Gentlemen, start your penguins
I wonder what Linus would think ?
The P4 architecture is not brilliant, pushing up the clock speed won't help the fundamentally stunted technology. There are major problems with the architecture, the worst of which is probably their decoder implementation.
The new architecture implements the U-V pairing and 4-1-1 in a nonsensical way. Multiple decoders have been eliminated and only one functioning decoder operates... the result of this is that just one instruction can be processed per clock cycle. Intel's theory was that the trace cache would eliminate the need to decode an instruction every clock cycle.
However, this falls apart when a set of instructions is put forward that does not go into the trace cache.... the processor must call upon the L2 cache or put all that code into memory to pull in another 64 bytes of memory for each instruction - and then decode the 64 bytes of code each time! The end result is that the P4 takes a lot more cycles to decode these instructions. Compared to the AMD Palomino XP processor (the fastest Athlon chip at the moment, in fact, the fastest X86 chip at the moment!), the P4 performance is a bit underwhelming.
The new Thoroughbred line of processors will introduce even better performance and completely blow Intel's offerings out of the water.
2DUP * ;
"Keep in mind, though, that you will not be able to use 64-bit addressing in 32-bit compatability mode with the AMD offering... you'll still be stuck with the 4 gig limit when running "legacy" code."
:-)
True, but with 64-bit OS's on Hammer, you can run 32-bit apps along side the 64-bit ones. Have a look at the work SuSE is doing.
http://www.x86-64.org
It's pretty impressive, and it's all working (on the simulator). I've seen 64-bit Linux boot and run X on a laptop running the simulator
I'm out of my tree just now but please feel free to leave a banana.