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Clockless Chips
iarkin writes "TechReview is running a very interesting
article about clockless chips.
Clockless, or asynchronous, chips work very much faster and consume less power than their synchronous equivalents (Intel hade some experiments on these chips back in -97, the results showed that the asynchronous chips were three times faster and consumed only half the power)."
"How Sun swerved to avoid Rambus"
http://www.theregister.co.uk/content/3/22279.html
More details on the CPU:
http://www.theregister.co.uk/content/3/22274.html
Sun press release:
Extends UltraSPARC III Chip Family Tree--First Use of Sun-Developed Asynchronous Logic Design in Chip's Memory Interface
At Sun Labs:
feature article
async research home page
The main problem with async. design is the asycnchronous part of it. In a typical computer, you have tons of parts that you use interchangably. These parts have operate at different speeds. How would two devices working at different speeds operate smoothly. Generally, this is very hard. But the thing is they can: But the devices themselves need to agree on a few things. But async. design is higly complicated because in a clockless environment you have to pretty much garauntee something like "I'll do this within 2 equivalent clock cycle." or have other types of signalling negotiation. You can't clock on a "clock" to do stuff. You have to clock on a "async" signal.
This is the problem in the large. When you go down to the chip level, there are tons of nightmares. There can be feedback loops causing race conditions that only occur at certain times. There are load problems that might increase complexity so much more than equivalent problems in a clocked design. Clocked design makes things a lot simpler and still designing a chip is extremely diffucult.
But the future I don't think is in clockless design, but "careful clock" design. For example, there are chips which are smart enough to disable sending the clock to certain part of a chip when it knows those parts will never be used. That saves a lot of power. There are chips which aim to spread the clock around carefully thus increasing the speed. And remember, almost 50% of the power in a chip is lost due to the wiring!
me.
As I understand it, traditional systems use a clock signal to let each stage of the pipeline know when the previous stage has completed. Each stage is designed to have few enough transisters that a signal has to pass through to guarantee that it will be done by the time the next clock signal arrives. Clockless systems instead design the processor such that at each step in the processing, the difference between a partial result and a completed result is self-evident. This requires more work, both in the design of the processor and in terms of transisters, but at the benefit of eliminating the clock (and many associated transisters) and any waiting between when the processor has completed a step and when the clock signal arrives.
Since dealing with the clock signal has become increasingly complex, instead dealing with not having one is becoming a more reasonable solution.
Actually, I bet there would at least some marketing cachet associated with a "clockless" chip. Remember a decade ago when CD player DACs went from 16 bits to 18 or 20 bits, then suddenly the coolest thing going was a "1 bit" DAC (i.e., a delta modulator)? The buying public will tend to go for whatever marketing decides is trendy.
The reason why asynchronous logic hasn't hit store shelves yet probably has to do more with implementational difficulties than marketing. I was taught synchronous logic design for my EE degree -- it's easier to design something when you know that results in remote parts of the chip are synchronized to the clock. When you looked at a timing plot for a circuit, it was usually pretty easy to debug because some parts of the circuit were clearly taking too long to execute their tasks -- and the solution was equally straightforward, decrease the clock speed. Designing for asynchronous circuits is probably much harder, since tentative results can screw things up. Furthermore, it's hard to imagine how some design techniques such as pipelining can work in an asynchronous environment.
Toronto-area transit rider? Rate your ride.
The IBM Power4 architecture uses a "Wavepipelined" interconnect bus. This is a clockless bus. I believe the Alpha 21384 was going to use this as well.
r dw are/datactr/p690.html
Too bad IBM won't sell the chips. They only sell the servers. Each die has 170 million transistors with 2 microprocessors per die! They package 4 dies in one package totaling 710 million transistors.
It kicks the snot out of anything Intel or AMD has.
Initial benchmarks show the SPECINT2000 and
SPECFP2000 at 808 and 1169 are comfortably ahead of the competition (2GHz Pentium IV was the SPECINT leader at 656, while Alpha 21264 @833MHz was SPECFP leader at 777).
Anybody have $450,000 to spare?
http://www-1.ibm.com/servers/eserver/pseries/ha
some intel guys were at async 2000. They mentioned the fetch/decode logic in the p4 was async.
No different than how graphics cards are released now. Yes, they actually have clock speeds, the most important being core and memory, but they aren't really marketed that way. Their names are artificial, ie GeForce Ti 500 ATi Radeon 8500, and the companies generally emphize the pretty sounding names for things like pixel shaders rather than talking about speed of the chip.