Slashdot Mirror
Intel's Big Chip
DeadBugs writes "News.com has an article about the size of the upcoming revision for the Itanium. The "McKinley" chip will be 464 square millimeters which would make it one of the largest ever produced. Most of this is due to the 64 bit registers and 3MB of Level 3 Cache. There is also a link to an article about "Chivano" an Itanium which will include concepts from the Alpha architecture"
Intel gets it right! Morce_Cache==Good_Thing. Was anyone else scratching their head over the 8k of level 1 cache on the Pentium 4?
Joe
i wonder if the oversized chip will lead to particular cooling difficulties(i.e. standard fans and heatsinks can't cool the entire surface area)...
lysergically yours
Is this the start of the manly "Mine is bigger than yours" battle?
Straight and to the point. Nice.
psmylie's dictionary: Godzillion (noun) Any number large enough to destroy Tokyo
Our new CPU is so big it will CRUSH the competition... No, really. We mean it quite literally :)
if Pentiums cost $50 to produce, will these cost 6x as much as a Pentium?
hmmm... sorry Intel, I'll stick to AMD till I hit the lotto, or have some other good reason to spend money like it was going out of style.
THERE IS NO DATA. THERE IS O
Sounds silly to me. By the time you get out to the 3rd level of cache, on a 1GHz core, there should be enough slow down that chip to chip interconnect will be adequately fast.
Either Intel has actually put research into this and discovered that it's a good tradeoff performancewise, or they've still got marketing driven engineering and someone said "wow! over 3 MB of on chip cache!"
Any guess on the wattage? Has Intel broken 100 Watts on their upward march of hot chips?
Start Running Better Polls
The Athlon chips i have are around 2-2.5 inches on a side, however, the die in the middle is quite small, i'd estimate it it be 200-250 square mm, so a 400+ square millimeter is huge, compared to that.
Anyone have any exact numbers for the chips? I didn't get a ruler out to measure it.
Yes, that would be just the raw silicon. Normal chips are typically under a cm^2 in size; everything else is packaging.
-WolfWithoutAClause
"Gravity is only a theory, not a fact!"Evan - needs to hit preview before submitting
Ace's Hardware has this bit with more information including links to an Intel presentation.
"Slide 22 of the presentation features a die photo of McKinley. The large 3 MB L3 cache is notable, and according to the presentation, it consumes 20% less area than traditional designs and is overall 85% efficient (~70% for traditional designs)."
And here's a story with the photo from that same article (no need to download 2.5 meg pdf...)
-Russ
Me
Actually the package is shown here and it looks pretty reasonable.
Just for some minor clarifications: The 464 mm squared is the area of the actual cpu die. Like the little square on top of an athlon. So 2 cm per side die is kind of huge for a processor. The actual processor out of the box would have to be much larger than previous models. Next, 3 MB cache sounds nice, but L3? It may be on die, but by that point the clock reduction probably makes it perform equivalently to a 256 k L1 cache, or a 512 or larger L2. Not that it won't help a lot for complicated instructions, and it's probably less expensive/difficult to engineer to hook a larger amount of cache to a slower pipeline than to add more cache deeper into the cpu's core. 64-bit cpu's will be important in the future, but only when compatible apps and OS designs become mainstream.
Way back when the 386 was hot stuff there was a series of mother boards that had a 64K of cache that was outperformed by a board that had 16K of cache.
How? The 16K board cache was four way set associative. This allowed for the CPU to determine in one clock cycle if the next instruction was in cache. The 64K cache design could not always do this. Thus it was often slower. Why not make the 64K cache 4 way set associative? Cost. The overhead in silcon and motherboard space made this impossible at the time.
For the article
Madison is expected to come out in 2003 and run between 1.2GHz and 1.6GHz, according to sources.
I wonder how Intel expects people to adopt Itanium-based processors considering
that x86 processors will be running at 4GHz in 2003.
Yeah, right. Intel is the big player. Right.
;)
My calculator's processor has 64 bit registers. You think i'm trolling? Check it out for yourself:
google search
There are a lot more (and more powerful) procs out there, but this one just seems more appropriate for intel bashing
Looking for people to chat about multicopters, coding, music. skype: gtsiros
..perhaps we're trying to get back to the good ol' days when you could walk around inside your computer....
or maybe they're taking the term "big iron" a little too seriously..
At that size, a smallish mug should fit nicely on it. No use wasting all that heat!
"464 square millimeters which would make it one of the largest ever produced....due to the 64 bit registers." 464^.5=21.54mm a side.
64bits/21.54mm=2.97 bits/mm
They've GOT to start using smaller wavelengths!
http://www.lostcircuits.com/cpu/hp_pa8800
8 70 0wp.pdf
Has 3Mbyte L1 cache and 32Mbyte L2 cache and
a transistor count of 300 million.
To quote:
"The HP PA-8800 L1 cache is probably the biggest L1 that ever existed so far with separate 750 KBytes of data and instruction cache for each core. This results in no less of 4 blocks of ¾ MB density each for a total of an unprecedented 3 MB L1 cache, physically twice as much as the combined L1+L2 on IBM's Power4. Accordingly, the transistor count of the HP-PA8800 is with 300 Million transistors almost twice as high as the 170 Million transistors of the IBM Power4 and results in a die size of 23.6x15.5 mm2 or 361 mm2. The L2 cache of the PA-8800 is off-chip and consists of four 72 Mbit "1 Transistor SRAM" chips developed by Enhanced Memory Systems.
http://www.cpus.hp.com/technical_references/PA-
has a roadmap of the hp-pa and Itanium chips so
really there is nothing new or exciting to report
that hasn't already been said 9 months ago.
... if you can't run the apps.
Intel x86 is restricted to 48-bit addressing (with segment registers), and practically 64GB with modern OSes. (http://linux-mm.org/)
If I want more than 64GB of addressable physical memory (which I do for some apps), then who cares if you can give me a 32-bit x86 running at 900GHz, it's not going to do diddly squat for me, since _going over the PCI bus_ for swap is going to kill me vs a 1.6GHz 64-bit processor. And since you need to go over the PCI bus just to get to a pseudo-disk stuffed with RAM, that solution is still bogus.
I see your point that this isn't what Joe Blow's gonna put on his desk. But the improved address space is definately a big win, and that's assuming that they can't ramp up the clock speed in a hurry.
Now that you mention AMD. It has been roumoured last week all over the net that intel has a backup plan, an P4 with 64bit extenstions
.18.
.18 and the next generation is on .13. note that this can make a differce of a factor 2 (13^2/18^2= 0.52)
os.opinion article
news.com
by the way, the amd hammer is expected to 105 mmm^2 on 130 nanometer (.13).
the current amd MP (palomino) has a die size of 129mm on
the original P4 has a die size of 217mm and is now at 150 mm^2.(with a bigger cache)
Note that the original article does mention the 424 size is on
Last I heard, Intel may have dug themselves a hole with Itanium. It's incompatibility with existing apps means that there is no desktop demand to drive economy of scale. Therefore the price isn't coming down and the price/performance is not improving faster than the older, "inferior" technology. How will they escape this death spiral?
sPh
The deal is this: larger die size chips are harder manufacture cost-effectively make because you get fewer good die per wafer. A wafer is a fixed size and costs the same to process, regardless of the number of functional die you actually get from it. So, the more die you fit on it, and the more die that actually work when you are finished processing, the lower your final selling price can be. Since the die size for this chip is much larger than "normal" and will be made in fabs that arguably will have the same defectivity rates, they will likely get less working die from a wafer than "normal" and thus their costs to the consumer will be larger.
You're missing the market. These chips, at least until they get them up to X86 speeds, aren't going to be used very much in the workstation market. These chips are going to be used in such places as database servers, where the current hack of 36 bit addressing used in Intel's current high end chips, the Xenons, is starting to fall apart. 64 bits doesn't mean much performance wise - in some applications, it's slower than 32 bits, but it means a world of difference when talking about storage. Instead of having hacks to get around the 4 gig barrier, one could, in theory at least, keep an entire database in memory.
Marxism is the opiate of dumbasses
184 square mm die size (prior to Athlon 800)
102 square mm die size (Athlon 800) ... source
Note that this article also states that: Intel has also incorporated a substantial amount of redundant circuitry in the processor, Krewell said. Chipmakers often use redundant circuitry to boost yields. Sometimes, circuits come out scrambled on a finished chip. If the manufacturer has put in two sets of the same circuits, the chip will function properly because it can use the second set.
You could have a dual Pentium machine and not even know it :)
I guess this redundancy is why the chip has gone up 10% in size in the last couple of months ... (see this article) which quotes:
One of the reasons for McKinley's bigger price tag, Krewell said, is that it will cover nearly 440 square millimeters in area--or more than twice that of the Pentium 4.
Package size is mainly driven by the need to get enough space to put all the connections onto it. Most of the reason for the McK being big isn't going to increase the connections - if you have 3Mb of cache you need the exact same address lines if you had 0 cache.
I wonder if AMD will start some sort of "size isn't everything" initiative.
Maybe they could offer some sort of conversion system, so that consumers can easily convert between centimeters and inches, and understand that AMD's new 1.5"+ chips perform about the same as Intel's 20mm McKinleys...
Nonono, his package, not his die size.
"If he thinks he can hide and run from the United States and our allies, he's sorely mistaken." Bush on bin Laden
The cache miss penalty is huge in IA64 because it can't reorder stalled instructions. That's one reason its performance is terrible on irregular memory-intensive applications (i.e., most server workloads). Anything that reduces the cache miss rate has got to help.
The question with an L1 cache of that size is how many cycles it takes to access the cache. It's easy to make a huge L1 cache, you just pay in increased access time. It's not impressive until we know the latency numbers as well as the size.
Is that an Itanium in your pocket, or are you just glad to see me?
Once upon a mid-day dreary, while I plodded, weak and weary,
Through an informative article about a truly massive core,
While I nodded, the newsfeed was slashdotted, suddenly there came a tapping,
As if FedEx gently rapping, rapping at my chamber door,
"Prob'ly FedEx," I muttered, "with boxes of reminders;
reminders of the law of Gordon Moore."
A feeling of having made the same mistake before: Deja Foobar
But there are segments of today's market that are willing to pay almost any price for a high-performance chip. These people will fork over a $1000 without blinking an eye if they think it will speed up their business.
Look at any commercial server available today. They're priced around $15000 - $20000. If chip prices go to $1000 instead of the $400 they're probably paying, that makes a difference of $2400, or about 12%, in a 4 way box. Even if chip prices went to $2000, it's a $5600 difference, or a 28% difference. If your processors are your bottleneck, then you've gained a lot of improvement for not-very-much delta in money.
Sure, a $2000 chip is out of reach for most home users today, but there is always a market for just about anything faster they can produce.
And there are enough crazed overclockers out there that'll spend whatever it takes to raise their frame rates on Quake III. It'll sell. It'll also drive the market to a new standard, which also sells chips.
John
Surely it's named after Mt. McKinley, the highest mountain in North America.
There should be a moratorium on the use of the apostrophe.
Max V.
NeXTMail/MIME Mail welcome
I find that journalism like the above is often the most effective way of communicating a point.
There should be a moratorium on the use of the apostrophe.
Max V.
NeXTMail/MIME Mail welcome
And just who or what do you think Mt. McKinley is named after?
General Relativity: Space-time tells matter where to go; Matter tells space-time what shape to be.
Obviously they aren't adding it for grins. I'm sure they did architectural studies that showed a performance gain comensurate with the cost. They probably chose that value after examing a number of possibilities and finding that to be the "sweet spot".
The enemies of Democracy are
Right, but I suspect that the processor has a lot more in common with the big chunk of rock (other than temperature -- Mt. McKinley is quite cold) than it does with a dead imperialist/jingoist figurehead.
That's like advocating equal rights on Martin Luther's birthday. Sure Martin Luther King was named after him, but still...
There should be a moratorium on the use of the apostrophe.
Max V.
NeXTMail/MIME Mail welcome
The latency is no secret. It is a 2 cycle latency cache. Pseudo 2-way set associative (you can load from an even and an odd row at the same time, but not 2 even or 2 odd)
Eventually you'll have 128MB of DRAM on chip. Why? Because it'd be faster. Closer memory is better.
Having the L3 on chip makes the same amount of sense as having the L2 on chip -- which is to say, lots. First, you can run the L3 at core clock speeds. No external bus is ever going to run as fast as pure silicon. This means that the latency is going to be much lower than for an off-chip L3. This means the average memory access time will be lower, which means better performance. Second, the bandwidth can easily be higher, since you don't have to pay with pins for extra data lines and, again, you're running at core speeds.
For those programs whose working sets fit into this amount of memory, the on-chip L3 is going to blow the doors off an otherwise equal off-chip L3.
The enemies of Democracy are
Maya 4 runs on x86 and PPC boxes too.. How does the ability to run Maya 4 make the Itanium powerful.. I'd be much more impressed if you'd told me that Intel had Maya 4 running on a 500MHz Itanium and it blew the doors off a dual Athalon or Dual 1GHz G4 box..
I want to see numbers.. How does the Itanium compare to the Ultrasparc 3 or Power4 processors? Does it play nicely in SMP configurations like the Power4? etc..
I think it does run older programs. In a simulation/emulation mode. Don't know much on how it works though...
It is never a good idea to make a product out of research project.
Well, that's a rather cold view. After all, where is progress going to come from if people don't try to make products out of research projects. Heck, we would still be using piles of stones to count our bushels of grain otherwise.
What you meant to say (and what the article said), is that 464mm^2 is size of the actual die size of the processor This includes the CPU and the caches. The CPU is a relatively small portion of the processor die, and noting there is 3MB of L3, the total cache may amount to 2/3 of the die size. The square on top of the athlon is also the entire processor die: cpu, caches and all.
Also, L3 cache can never perform "equivalently" to L2 or L1 cache unless it runs at core speed. And I can tell you now, it doesn't -- or they wouldn't need L1 and L2. The L3 cache probably runs at something like 10 access cycles or more. It's not difficult to engineer 10 access cycles into any pipeline -- it's impossible. Which is precisely why it's not L1.
I'm quite sure the engineers at Intel have done their modeling homework and determined that however fast the L4 memory may be, the L3 will improve performance by that much more.
Remember, this processor is not meant to go on you or any other Joe Sixpack's desktop. It is meant to sit inside the workstations on the desks of engineers and in the racks of high-bandwidth servers. These platforms are specifically designed to run hundreds of tasks simultaneously and handle staggeringly high memory bandwidths. It has nothing to do with "complicated instructions." The L3 exists for swapping out large pages of memory in large bursts from a significantly larger sized L4 memory (think on the order of 100's of GB) from L5 memory (local drives and SANs) that has an incomprehendable virtual memory space.
This has absolutely nothing to do with mainstream. I'm quite certain an OS already exists that will run on the platform. An IA-64 Linux is well under way (try http://www.linuxia64.org) and you can bet that Compaq, HP, Dell, and Intel have put a total of more than 100x your lifetime earnings into developing software for that platform.
Intel could not care less whether you or 99.9% of the /. readers out there ever buy an IA-64. They don't give a crap about your market segment, but I'm sure if you want to drop $10K+ on a IA64 workstation, be my guest. Your choices are limited. Either choose IA64 or UltraSparc. Or maybe if AMD ever gets a design win, you might get a chance to buy a Hammer box.
I've never been able to figure that out.
"... also announced was the new 'Chicanium', which combines the 200Mnerdz power processing of the Itemium with the sexual prowess, digitally extracted, of a cheap Tijuana hooker and her little brother. Release date, 2002."
(The processor, not her little brother.)
; -- the corruption of government starts with its secrets. a truly free people keep no secrets. --
You're absolutely right. On top of that, the yield is going to be ridiculous. See, a wafer has defects. To get a good approximation, imagine a 6 or 8-inch target on which you shoot darts. The best wafer processes give you about half a dozen defects, and boy are these wafers expensive. Each time you have a defect, the chip that is engraved on this spot will be faulty and be rejected.
You can easily see that for a given defect density, the same wafer will have approximately the same number of bad chips (even if you split hair with the probability of getting two defects tiled by the same chip). With a small die, you can easily squeeze more good chips around defect spots. One more reason why a small die size is key to yield.
So this chip is going to cost a freaking fortune to manufacture, especially with the bleeding edge process they are boasting.
But wait, it does not stop here. 22 x 22 mm chips, huh? Assume that the clock tree (i.e., the tree-like circuit that distributes the clock signal in the chip) has a longest path of 10 mm. That's already the heck of a skew on the signal. And you can easily increase that longest path estimate by 30-50% because signals can't propagate in straigth lines, they have to be routed along structures. This alone guarantees the clock speed will never go as high as competing chip's frequencies.
This is a sheer waste of engineering resources. For a processor, such a size is just not practical.
Conclusion: This thing is a demonstrator. It will never fly. It's not meant to. And even for a demonstrator, it's too bulky.
--
Mad science! Robots! Underwear! Cute girls! Full comic online! http://www.girlgeniusonline.com/
For most people, 64-bit arithmetic isn't critical - most applications don't deal with ints larger than a billion, though us crypto people who do lots of bignum math are happy to get a 4x speedup. Otherwise, the quality of floating point implementations is likely to be more important. So it would be possible to get by with 32-bit arithmetic and 64-bit addresses, like we did with the Motorola 68000's 16-bit-ints and 32-bit registers and addresses - but that was also somewhat tacky, and led to *lots* of bugs in code that assumed ints and pointers were the same size, though perhaps we've evolved enough past K&R C that newer software won't make that mistake as often.
A real problem this time around is that the C language and its relatives really do like 32-bit integers, and many of the Unix system calls also assume 32 bits. If you make the native int/pointer sizes 64 bits, there's a lot of stuff that will probably break. What kind of experience have people had running code on DEC Alphas and other real-64-bit chips?
Bill Stewart
New Fast-Compression-only CPR http://preview.tinyurl.com/dy575ks
Of all the media bull I've heard about the 64-Bit Intel/AMD chip, I've yet to hear ONE SINGLE person claim that the new chip will be somehow better than the Alpha.
t ml
Tell you what. Since all the apps need to be fixed (or at least recompiled) to work on 64-bit processors anyhow, why not just go the route of porting everything to the Alpha? We could use this to finally get the hell away from Intel's terrible chipset.
And for all of you that think the Alpha will be dying soon, there are plenty of companies other than Compaq with Alpha products that are far better quality than Intel, and will likely be cheaper as well.
http://www.microway.com/products/ws/alpha_21164.h
Slashdot gets worse every day... Pipedot: News for nerds, without the corporate slant
Next, 3 MB cache sounds nice, but L3? It may be on die, but by that point the clock reduction probably makes it perform equivalently to a 256 k L1 cache, or a 512 or larger L2.
A fundamental rule of building caches is that a larger cache is slower and dissipates more energy per lookup than a smaller cache. This is why multilevel cacheing exists in the first place (otherwise we'd just have a huge L1 cache - and before you mention it, due to architectural sneakiness, HP's giant L1 cache isn't really an L1 cache).
So, you can't just spend the L3 area on making a bigger L2. You'd end up with a slower, hotter L2, which could easily _degrade_ performance.
As long as the L3 cache is faster to access than main memory, it'll be useful for some things. Whether it'll be useful for *most* things is another issue. This depends on the "working set" of the applications you're running (how much memory they repeatedly access). I guess Intel's banking on working sets being larger than most caches.
Another possibility is that they're testing the cache architecture for use in future SMT or CMP designs (both of which would have multiple independent executioin contexts running). If you're running multiple *independent* contexts, the working set grows with the number of contexts.
EETimes has a nice article with a good graphic comparing the internal workings of the Itanium vs. McKinley ... a good level of detail: 10 vs. 8 pipeline stages, differing bus widths and speeds, execution units, etc.
The article also talks about other intel innovations disclosed at the International Solid-State Circuits Conference
HIV Crosses Species Barrier... into Muppets
Anyway, with 3MB of onboard cache, I doubt the I/O pads are to blame for the large die size of this CPU.
I've never seen a good explanation of how Alpha concepts could possibly benefit the IA64 architecture. Usually it's only talk about HyperThreading, which is just Intel marketspeak for SMT (Symmetrical Multi Threading) a feature long ago promised for the Alpha and PowerPC product lines -- and a marginal improvement more related to packaging and manufacturing than an architectural feat.
I fail to see how Alpha could benefit IA64, since the fundamentals underlying the two different architecture are quite opposite -- changing IA64 to be more like Alpha would give us probably a worse Alpha or a not so bad IA64, but would fail to realize Alpha's promise of a clean, balanced architecture, and so would be mediocre compared to PowerPC, perhaps UltraSPARC and probably to what Alpha, PA-RISC and MIPS could have became weren't them orphaned.
In fact, it seems to me that even a hypothetical SMT StrongARM would run faster and cooler than an equivalent cost and size IA64. But that's only my quite uneducated guess.
Leandro Guimarães Faria Corcete DUTRA
DA, DBA, SysAdmin, Data Modeller
GNU Project, Debian GNU/Lin