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Boosting Battery Life For RISC Processors
prostoalex writes "National Semiconductor and ARM Holdings will jointly develop the power management solution for RISC chips, that they estimate will improve battery life by 25-400%. The target date of the first sample product is Q2 2003." My old Tadpole laptop sure could have used this. I counted myself as lucky when I got a whole 45 minutes out of a battery.
[BLOCKQUOTE]
According to the article:
Arm's Intelligent Energy Manager solution implements advanced algorithms to optimally balance processor workload and energy consumption, while maximizing system responsiveness to meet end-user performance expectations.
Transmeta's only claim to fame for their chips was using software to reduce power consumption, and it worked -- obviously, the Intelligent Energy Manager is just a ripoff of Transmeta's design. Linus should sue. [/BLOCKQUOTE]
Umm, no? These aren't CPUs used in computers and laptops.. these are used in handheld devices and embedded applications. I develop for ARM personally and the "algorithms" (note: they do not say software) is simply silicon embedded within the processor.. not software that runs on the processor itself.
As the poster mentioned, I doubt this will affect any laptops. I don't know of any that run off ARM cores.
http://www.arm.com/news/powerwise1111
They're basically targetting mobile phones and similar embedded systems like PDAs, because this is where ARM's main market share is at the moment. They say that they're looking at a more system-wide approach than is currently used, and they want to standardize the embedded software/hardware interface as part of this.
Also, note that "samples available Q2 2003" doesn't necessarily mean actual silicon. ARM doesn't make chips, they license their designs out to other companies which use them as a basis for an actual chip, so a "sample" quite likely means a software simulation. Actual devices which use this technology probably won't be around until 2004 at least.
That is one method of doing it (turning of clock trees to shut down a set of gates). One other way is to adjust the supply voltage and clock frequency to the CPU core. As ARM allready utilizes clock gating, the voltage/frequency technique is a very viable option for even more efficient CPUs. I'm usually not a big fan of Intel's, but look at their XScale and the measures they've taken to preserve energy. I have to say that I'm impressed!
"always lagged in the floating point benchmarks"
This lagging is not due to flaws in the ISA (instruction set architecture). Todays CISC cpus (atleast the post-Pentiums and Athlons) are RISCs with a CISC shell.
The expansion of instruction sets have two drawbacks: 1) bloated designs and 2) more and more complex compilers. That is why RISC is leading the way (in a CISC suite) and CISC is degraded into keyboard controllers etc.
In typical usage, there is a lot of time that the CPU is doing nothing. Design one that can take snoozes for as little as a millisecond at a time with insignificant latency and you can save a lot of power.
I'd say that SPARC VI and VII will be more innovative (article here). I must say that ARM is not the *only* architecture used for innovative CPU designs. In academia I've seen both MIPS, SPARCs and custom designs to show/implement special innovations (vector co-processors, async logic, etc.) Usually small subsets of commersial CPUs are used for the truly innovate designs. (IMHO)
> Usually small subsets of commersial CPUs are used for the truly innovate designs. ...As well as in my humble opinion - could not agree with you more.
And you are right about SPARC, MIPS as well. In addition to some interesting tech features, Sparc has the advantage of being an (almost) true clear and open architecture, rather than a concrete chip design. If I remember correctly, MIPS is great in its context-insensitive structure (no condition bits). Then Crusoe (and PowerPC, for that matter) are great in that they were intended for emulation, but allow native code, thus migrating away from the obvious enventual x86-dead end.
However, a feature that only ARM and Transmeta incorporated in design (from the beginning), is the performance / transistor -ratio. Being a low cost 32 bit alternative to the 16 bit dominated market of the late eigties, Acorn's choice for a RISC architecture was probably a pragmatic matter, rather than a philosophical one. And inside an Archimedes desktop computer it did not primarily minimize power consumption, but rather maximize performance / research cost.
Well anyway. Ever since Acorn let go of the ARM processor, it's been pretty popular in actual devices as well as in design experiments.
> My old Tadpole laptop sure could have used this.
I think the type of RISC processor might have something to do with the power consumption. ARM has always concentrated on frugal at the expense of fast.
Virtually serving coffee
Each CISC instruction is transformed into a set of RIST instructions. These u-ops (micro-ops, Intel lingo) are then dynamically resceduled and register renaming and all such techniques are applied. I don't know if the P4 can manage out of order comitting, but the instructions are issued and executed in arbitrary order.
This gives that the internal state of the CPU will be complex and dynamic. This does however not indicate the there are no optimizations that can be made by removing the CISC abstraction layer.
For example, all fp operations on x86 CPUs emulate a stack based maths co-processors, which is implemented with real registers. Direct access to these can improve quality of the code tremendeously. When saying this, one must remember that the P4 bashes most CPUs in fp benchmarks, and can, most likely be even better with direct access.
To sum things up: I do not understand how you can say that a CISC layer does not slow the system down and that the ISA is "almost irrelevant". I have interpret that as pure ignorance.