Slashdot Mirror
Boosting Battery Life For RISC Processors
prostoalex writes "National Semiconductor and ARM Holdings will jointly develop the power management solution for RISC chips, that they estimate will improve battery life by 25-400%. The target date of the first sample product is Q2 2003." My old Tadpole laptop sure could have used this. I counted myself as lucky when I got a whole 45 minutes out of a battery.
I once had this link to research done on cpus, which are designed from the ground up to be VERY low power. Consider this: they saved power at the *gate* level!
Looking for people to chat about multicopters, coding, music. skype: gtsiros
In line with the low-power paradigm gaining momentum within CPU designs, asynchronuous design is often mentioned in the context of battery life. Apparently, the ARM processor seems to be the (only) architecture used for innovative CPU designs.
Is this really the case, and if so, why? (Obviously CISC architectures are far too complicated to fine-tune in a drastic manner - other than building a Crusoe-like RISC chip and emulating the whole thing.)
Moreover, is power consumption (and not primarily performance) after all those years, going to be the criterium that's going to decide the RISC-CISC issue in favour of RISC?
It is a simple question of market laws. The x86 architecture is the ruling class, therefore it gets most of the research money, and as a results has the fastest running processors.
When the ARM came out, it blowed the 386s (The top x86) and 68020's out of the water. We were talking 3-4 times faster. And when the ARM3 came out with it's cache, it really kicked 386 ass.
And remember the Alpha? Another RISC design that was way ahead the rest. The only one left is the PowerPC family, still holding on to the x86 juggernaut.
And programming the ARM was a bliss. 13 general purpose registers, the barrel shifter. (Do a arthimetic and shift in the same instruction) Conditonal branching... It was a real joy. The x86 assembler is what programmers do in hell.
J.
I think it's interesting to note that they use cellphones as a typical example of improvement.. however, the micros in cellphones use a fraction of the power. The vast majority of power is consumed by the RF transmitter, as evidenced by the amount of battery life you get while making a phone call as opposed to standby operation.
25 to 75% baseband power savings probably amounts to no more than 10% total improvement on battery life. Marketing fluff?
Very true. Look at this for a laugh. A minimal installation will take approx. 120MB of disk space and 40MB of RAM. I can't help wondering what they are doing over there (at M$).
How is it then that we do not see standard CPUs with custom portable devices?
You are correct when you say that backlit displays, disk drives, CD players and such consumer much power, but so does also all transistor switches (from on to off and the other way around). The sheer number of transistors and the incredible frequency of these switches makes the CPU one of the power hogs in a portable system today.
As an old Acorn user who switched to Mac back in 1998, I can safely point you to this fact without appearing anti or pro Apple/IBM/ARM.
"ARM Company Milestones: ARM History - 1985 - Acorn Computer Group develops the world's first commercial RISC processor"
The points were indicating the drawbacks from expanding instructions sets (further). I understand that it can be read as being a part of the conclusion, but I did not intend it that way.
When discussing what ISA the compiler sees I can't help wondering how efficient code a compiler could emit if it gained access to the risc cores of a P4 or a Tbird? Maybe it is time to introduce another mode (after protected mode of the 386): RISC mode (or, as intel's marketeers would call it PowerMode(tm) :])
I have to agree that the P4 is a monster when it comes to transistor count and the PowerPC and the derivates are amazing. However, there will always be idle parts of the CPU core that can be shut down during different periods (for example fp ops.). Just since you have a simple (as in beatiful, optimized, etc) architecture does not mean that you should not further improve it by using state of the art optimization methods.
Your best example was the FP stack. However, does that not internally become traces that can access the FP registers in arbitrary ways? Can the traces not eliminate extra spills, dups, swaps, and other artifacts of stack-based computation? If it doesn't currently do so (which would surprise me) then I would expect that a future version of the Pentium certainly could.
I say the ISA is almost irrelevant because the compiler's optimizations occur with RISC-like instructions, and then the actual execution (u-ops) occurs with RISC-like instructions. The CISC ISA doesn't actually do anything except communicate the former to the latter. Certainly there is overhead for translating the ISA to u-ops, but hot code is usually executed many times, and so the translation cost is amortized over a large number of iterations, making it negligible.
AMD's whitepapers on x86-64 claim that the x86 ISA is a good one for their moden processors because they get the code density of CISC with the register usage and ABI models of RISC. Clearly they may be biased because they have a technology to promote, but I think their arguments have merit.
Perhaps you could give an example of how the P4's internal u-op traces are sub-optimal because of the CISC ISA?
Patrick Doyle
I mod down every jackass who puts his moderation policy in his sig. Oh, wait a sec....
Risc Os 5 in a new true 32 bits version will soon be available for Xscale CPU desktop systems. It could mean a second life for an OS that was developed by Acorn at the same time when they started the ARM development. It shows that ARM isn't just for embedded applications. The lean and mean approach of ARM has its equivalent in Risc Os. There's a trend towards desktop systems with less heat and sound, energy saving isn't bad then.
http://www.riscos.org/cgi-bin/news?days=
http://www.iyonix.com/Launch/winapc1.html