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Single-Chip Linux Computer

goombah99 writes "Axis Computer has announced a single-chip Linux-based computer that integrates 2MB Flash, 8MB SDRAM and an Ethernet transceiver into a single chip with a 27mm x 27mm footprint. 'Just add power to the chip and you have a Linux computer with network connection.' It runs the Linux 2.4 kernel without any patches. The announcement says the chip is 'available' but the tech specs are labeled as preliminary, and the order form on the web site is broken, so it's hard to confirm if it is out yet or not. Some specifications in html and pdf are available at the company's web site."

17 of 217 comments (clear)

  1. Re:enough of the 1990 hardware!! by nick-less · · Score: 5, Informative

    but really, serial ports? parallel ports? i'm not too sure that the scsi is going to win them any points either, but what the hell. they might have well integrated a video controler, an audio controler, and a 9600 baud modem to boot!

    Well, I think they target embedded applications and not laptops here. Most embedded applications don't need sound or video capabilities and most engineers love to have serial and parallel I/O, because of their simplicity.

  2. Cell computing anyone? by The_Mutato · · Score: 1, Informative

    Lots of people have heard that the PlayStation3 will have "Cell computing", which is when they have lots of tiny cpu's clustered together each doing an extremely small part of the computing process. This will make programs using threads REALLY fast. I hope they have a cell computing device (like a cell computing PDA) made out of some of these things!

    Imagine a Beowulf cluster of these things!

  3. Re:enough of the 1990 hardware!! by Anonymous Coward · · Score: 2, Informative

    In embedded world, you want minimalistic hardware. USB requires a microcontroller with USB stack just to talk to it. It is far easier to use serial port and probably 3 lines of code to talk to a serial port. Parallel port can be interfaced pretty much directly to keypad, small character LCD, relays etc. Can'tt say the same for USB without yet another microcontroller.

  4. Open computer by brejc8 · · Score: 2, Informative

    I am about to work on an FPGA single chip computer. Taking an open MIPS(ish) core and connecting it up to some peripherals.
    The best thing about its is that it will be completely open.
    Opencomputer will start as an FPGA but I am hoping to find a good excuse to manufacture it along with an asynchronous version and make my self a fully open PC.

  5. How do we know this? by bconway · · Score: 2, Informative

    It runs the Linux 2.4 kernel without any patches.

    Just to break out the tinfoil, how do we know? I think that if I were to make Linux work on a device my company produced, I'd claim it worked without any patches, and thus only point people to a vanilla source, and not have to release any of my changes for my competitors to see. I'm no fan of the GPL (and bash it regularly), but this seems like a viable tactic. Saying that you can't get the code to work on their chip doesn't seem like much in the way of indisputable evidence that they altered the code, either.

    --
    Interested in open source engine management for your Subaru?
    1. Re:How do we know this? by exolon · · Score: 2, Informative

      It runs on the 2.4 kernel without patches because the CPU architecture and HW drivers have been in the vanilla 2.4 kernel for a long time (see arch/cris).

      The developer.axis.com site also has the additional tools you need for developing like compiler packages and flash downloading tools etc.

  6. Is shipping, and Bluetooth is avail, too by diegoq · · Score: 5, Informative

    It is available.

    The chip itself is $40. The eval board for the ETRAX 100LX is available for $299 as well as a version with bluetooth for $495.

    Finally, the order page for both of these is at https://www.axis.com/shop/technology.htm.

    --
    --Tim
  7. Article in Case of Slashdotting by Anonymous Coward · · Score: 0, Informative

    Axis Launches Complete Linux Computer on a Single Chip
    -- 12/26/2002

    Chelmsford, Mass. - Axis Communications, a global leader in network technology, announced today the availability of the AXIS ETRAX 100LX MCM 2+8, a new generation system-on-a-chip that integrates 2MB Flash, 8MB SDRAM and an Ethernet transceiver into a single chip with a 27mm x 27mm footprint. The chip, which is designed for networked devices such as wireless access points, digital video recorders and access control and security systems, enables developers to reduce costs in both the design and production cycles.

    By integrating the most common components used in a standard ETRAX- based hardware design, nearly all of the mandatory components for building a networked device are included in an extremely small chip. The integrated approach makes the ETRAX 100LX MCM a competitive choice for developers needing to improve efficiency in the development process. With the most time- consuming components already integrated into the chip, the ETRAX 100LX MCM enables developers to shorten the time to market and focus on product development.

    The new chip utilizes a technology that enables the integration of naked dies (chips without their capsules), to provide smaller and more cost-effective networked devices. By using this chip in designs, developers will significantly decrease hardware development time and greatly reduce the risk of errors in design.

    The ETRAX family of processors is intended for Ethernet-connected embedded systems running Linux. The software development kit for the ETRAX 100LX family is based on the standard Linux 2.4 kernel, and developers can easily support applications available for standard (PC) Linux. The ETRAX processor also includes a Memory Management Unit (MMU), which enables memory protection and full software compatibility with Linux applications.

    Volume shipments will begin by the end of December 2002. Samples have already been delivered to more than 20 reference customers who have completed new product designs or are currently working on them. More information and technical specifications on the AXIS ETRAX 100LX MCM 2+8 can be found on http://developer.axis.com/products/mcm /.

    And here are the specs:

    AXIS ETRAX 100LX

    Design goal:

    Designed to meet demands for low cost, easy implementation and superior network performance, the ETRAX 100LX is Axis' sixth-generation optimized system-on-a-chip solution for putting peripherals on the network. The ETRAX 100LX was developed using 0.25m ASIC technology with the best price/performance ratio available today.

    The sixth generation of the chip was specifically designed with Linux in mind and includes an MMU (Memory Management Unit) for that purpose.

    The latest edition of Axis' ETRAX chip was designed with a number of basic criteria in mind:

    Support higher bandwidth networks
    The increasing use of network topologies such as Fast Ethernet has created the requirement to support faster speeds in Axis products. To achieve a higher data transfer rate, both the CPU and DMA functions were integrated. This has enabled Axis to simplify the design, reducing necessary program memory by a factor of 30 percent over a typical 32-bit RISC processor while lowering the cost.
    Optimize performance
    In order to saturate a 100 Mbit network, Axis created a packet burst architecture featuring
    a zero-copy network DMA structure. The integration of this structure into the overall architecture results in a network device "system-on-a-chip" capable of supporting high performance while reducing the load on the 100 MIPS-rated CPU.

    The overall approach is one suited for connectivity rather than computation, supports data transfer rates of up to 200 Mbit/s (100 Mbit Ethernet full duplex), as well as a wide range of network device applications
    Reliability, stability and rapid development
    An ASIC approach provides the ability to build in functionality typically found in high-end
    communications devices. ETRAX 100LX-based products and embedded systems include a number of management utilities such as:

    A patent pending bootstrap function so units can be booted remotely over the network, even if they have no program code in memory
    A patent pending logic analyzer function for cache monitoring and real-time debugging
    Watchdog timer providing self-diagnostics and increased reliability
    A consistent development environment: The ETRAX 100LX is backwards compatible with the ETRAX 4, in order to ensure that OEM partners are able to preserve their earlier development investments

    Read more about the history behind ETRAX

    Performance:

    The innovative 100 MIPS 32-bit RISC design delivers compact code and exceptional price/
    performance at low power consumption. An 8-kbyte on-chip cache helps to take full advantage of the CPU performance.

    Rich variety of interface options:

    ETRAX 100LX has almost everything you need included

    32 bit RISC CPU core
    10/100 MBit Ethernet controller
    4 asynchronous serial ports
    2 synchronous serial ports
    2 USB ports
    2 Parallel ports
    4 ATA (IDE) ports
    2 Narrow SCSI ports (or 1 Wide)
    Support for SDRAM, Flash, EEPROM, SRAM, ...

  8. Re:Is it an ARM? by brejc8 · · Score: 4, Informative

    It only says its a 100 MIPS processor. (Million Instructions Per Sec)
    The MIPS has 32 registers.

  9. Includes perifirials and much more by goombah99 · · Score: 2, Informative

    from the specifications page
    ETRAX 100LX has almost everything you need included

    * 32 bit 100MIPS RISC CPU core
    * 10/100 MBit Ethernet controller
    * 4 asynchronous serial ports
    * 2 synchronous serial ports
    * 2 USB ports
    * 2 Parallel ports
    * 4 ATA (IDE) ports
    * 2 Narrow SCSI ports (or 1 Wide)
    * Support for SDRAM, Flash, EEPROM, SRAM, ...

    Just add power and and ethernet connection.
    Quite an impressive package. Though in practice you would need to add more memory. But think about it, in the space of about 1/2 cubic inch you could cram memory, the chip, plus say a Microdisk. Expand that to the size of an IPOD and you could put in a lot of stuff, incuding the power supply

    I'm not exactly how fast 100MIPS when comparing a RISC to say and Intel CISC that takes many clock cycles to complete on instruction. I'm assuming its probably slower than a 2 Ghz Pentium, but fast for an hand held.

    <b>What Gets interesting is this: it dissipates 0.35 watts (typical)!!!!! </b>Let me say that again. It dissipates 0.3 Watts for 100MIPS. compare that to a typical Pentium Computer in the hundreds of watts range for a Gigahertz. This means you could have 600+ in a single 1U chasis dissipating the same amount of heat.

    Time to really start thinking about parrallel software and computer deisgn. For easily paprlizable problems 600 of these ina 1U would destroy an entire rack of Pentiums while disspating so little power this could be just slipped under your desk, not in cooled computer room. Oh did one of the chips burn out--who cares, there's only 599 more.

    --
    Some drink at the fountain of knowledge. Others just gargle.
  10. Re:Is it an ARM? by ntp · · Score: 5, Informative

    Nope, you're all wrong. It uses the CRIS architecture. See here for the architectural description.

    --
    I control the time!
  11. A MCM is not a single chip by Internet+Dog · · Score: 4, Informative

    The title is misleading. The device is a multi-chip-module, not a single chip computer. They have packaged a number of chips in a very small package, but it is not a single chip. A MCM will cost more to manufacture than a true single chip computer because it requires a ceramic substrate to be manufactured with very small trace widths connecting the chips that are placed on the substrate.

  12. Re:So.. what kind of CPU is it? by andy4us · · Score: 2, Informative

    It's a Cris architecture, if, you expand a recent kernel or 3.2 gcc source you'll see a bunch of stuff for cris. I have one of their development boards which doesn't use the MCM but is a 100LX based system.

    Andy

  13. Hey moderators!!!! this is not off topic by Anonymous Coward · · Score: 1, Informative

    This is rated -1 off topic. Get a clue. If you think this is off topic, you don't know what you're talking about.

    FPGA SoC prototyping is _exactly_ on topic with this discussion of the Axis chip. If you want to see RTL for an SoC you can download today, synthesize for an FPGA and run (uC)linux on, look one of these places:

    www.gaisler.com (SPARC core)
    www.opencores.org (OR1200 - OpenRISC)

  14. No RISC by Euphonious+Coward · · Score: 3, Informative
    If you read the specs on the CPU carefully (which I did, a couple of years back) you discover that it is not really a RISC at all, by any definition of the term. The architecture is very similar to the VAX, in fact. They just call it a RISC because that once sounded more advanced. Today, of course, calling an architecture RISC makes it seem kind of backward, but they've been saying it long enough that it's probably too late to change.

    This is not to say that the designation means much any more... people have discovered how to make the most horrendous instruction sets (read: x86) go fast with only a million (!) extra transistors or so. This CPU doesn't have those, but what matters is that it's fast enough.

    Still, it's amusing because half the complexity of the instruction set (and a substantial parcel of the chip) will never be exercised by any compiler. It's there as a sort of homage or shrine to machines from the days when programs were written in assembly language, and machines were marketed on how fancy the instruction set was, regardless of how it slowed the machine down.

    The CDC machines were exceptional: Seymour Cray really understood. Also, in the '60s, some people at IBM built the 801, which evolved into the PowerPC. The rest of the industry didn't catch on until the Stanford RISC people made their big splash.

  15. Re:Linux in under 2MB?? by Koos+Baster · · Score: 3, Informative

    Right so. 2MB should be enough for anybody! ;-)

    Red Hat should take notice, but still it's importatn that Red Hat is just as Linux as this tiny system is. And, there is a point in Linux being able to downsize into less than 2MB. Although Desktop Linux is not and does not allow for the same applications as embedded linux, there is a real virtue in sharing the codebase between these two. (Or desktop and webserver, cluster or grid server for that matter.) Although developers may not always agree on the direction the developments should take, together they provide for an open environment that is scaleble, and in escense is very lean. This is something Microsoft can never touch upon with Windows CE/PocketPC/whatever.

    That's why I think this one-die embedded linux system is indeed a a-good-thing (tm).

  16. Righto - CRIS is *not* a RISC, that's for sure! by bap · · Score: 2, Informative
    The CRIS CPU architecture seems reasonable for an embedded CPU optimized for code volume, but to call it RISC is outrageous. There is nothing RISCy about CRIS. In fact it is pretty much a classic CISC, highly reminiscent of the VAX.

    Look at the complex addressing modes and variable-length instructions: hallmarks of a CISC. To quote chapter 2 of the documentation,

    2.3 DATA ORGANIZATION IN MEMORY ...

    Data can be aligned to any address. If the data crosses a 32-bit boundary, the CPU will split the data access into two separate accesses. The use of unaligned word and dword data will thus degrade the performance.

    ... 2.4.1 Addressing Modes The CRIS CPU has four basic addressing modes. These modes are encoded in the mode field of the instruction word. The basic addressing modes are:

    • Quick immediate mode
    • Register mode
    • Indirect mode
    • Autoincrement mode (with immediate mode as a special case)
    More complex addressing modes can be achieved by combining the basic instruction word with an addressing mode prefix word. The complex addressing modes are:
    • Indexed
    • Indexed with assign
    • Offset
    • Offset with assign
    • Double indirect
    • Absolute
    The addressing modes of the CRIS CPU are

    Assembly syntax; Addressing mode
    i, j Quick immediate
    Rn Register
    Pn Special register
    [Rn] Indirect
    [Rn+] Post increment
    x, u Byte immediate
    xx, uu Word immediate
    xxxx, uuuu Dword immediate
    [Rn+Rm.m] Indexed
    [Rp=Rn+Rm.m] Indexed with assign
    [Rn+[Rm].m] Indirect offset
    [Rn+[Rm+].m] Autoincrement offset
    [Rn+x] Immediate byte offset
    [Rn+xx] Immediate word offset
    [Rn+xxxx] Immediate dword offset
    [Rp=Rn+[Rm].m] Indirect offset with assign
    [Rp=Rn+[Rm+].m] Autoincrement offset with assign
    [Rp=Rn+x] Immediate byte offset with assign
    [Rp=Rn+xx] Immediate word offset with assign
    [Rp=Rn+xxxx] Immediate dword offset with assign
    [[Rn]] Double indirect
    [[Rn+]] Double indirect with auto increment
    [uuuu] Absolute