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AMD's Next Generation Processor Technology
Esekla writes "AMD has released info about their upcoming processor technology. The press release claims that they're producing circuits that run 30% faster than any other published benchmarks using "Fully Depleted" Silicon-on-Insulator and AMD's metal gating technology and actually has a good bit of technical detail for a press release."
As you may or may not know, IBM originally developed Silicon-on-Insulator technology and licensed it to AMD. Here is the whitepaper: http://www-3.ibm.com/chips/bluelogic/showcase/soi/ soipaper.pdf
This is the same technology that was used to make the Power4 processor, and will also be used to make the upcoming PPC970: http://www-916.ibm.com/press/prnews.nsf/jan/06C1F2 11F9B1C24B85256ADF006163AF
AMD has recently built a new state-of-the-art fabrication facility in Dresden to produce the chips, known as "Fab 30": http://www.anandtech.com/cpu/showdoc.html?i=1773
I hope together IBM and AMD will continue to update their manufacturing process to keep on par or perhaps once again surpass Intel.
Wow, AMD sure is pumping out those chips fast. It seems like just yesterday they were announcing the Barton core. Now they've already got a new chip. In my experience, you should never buy the newest stuff anyway. Wait a few months, then buy it when the price goes down.
You donâ(TM)t have to worry about your current (pun intended) non-fully-depleted silicon oxide chips.
So you donâ(TM)t need to go shopping for a lead ATX case.
I think the full depletion increases insulation so the layer can be thinner.
Esteem isn't a zero sum game
Polysilicon has been the gate material of choice because it is much easier to process. However, metal would reduce the resistance of the gate. (The gate acts like a little capacitor, and the resistance of the gate affects the amount of time it takes to charge up and discharge, which affects the switching time.) I think the processing ease of Polysilicon is lost when you don't use Silicon dioxide as the gate material - for example, if you used a high-K dielectric. I don't know if metal is inherently more compatible with high-k materials, just that it's less compatible with SiO.
They also mention the metal gives a "tunable work function" (probably by adjusting the silicon/nickel ratio), which I would guess would change the turn on voltage of the transistor. Tuning the turn on voltage could certainly tweak up the speed a bit.
It's not wasting time, I'm educating myself.
Intel getting smacked around? I think it's a pretty even day, afterall intel announced More Advanced Triple-Gate Transistor Design One Step Closer to Production today.
There are Xeon MP procs w/ 2 Meg Caches. I'm not positive but I believe that opteron also has a 1 Meg Cache. If your looking at doing something that high-end there ARE options out there. They just arn't cheap.
Dopant profile and gate geometric effects on polysilicon gate
Gate Length Dependent Polysilicon Depletion Effects
Also EETimes has another interesting article with more information about AMD's presentation at the 2003 Symposium on VLSI Technology in Kyoto, Japan.
Metal gates have 4 main advantages in advanced CMOS transistors:
(1) The gate resistance is reduced. This lowers the switching delay in some cases. Remember that the delay is proportional to the product of the resistance and capacitance (the 'RC' product).
(2) In polysilicon gates, the free carrier density is very high (1E20 carriers per cubic cm). Even so, under high electric fields that are needed to switch a transistor, there is a small depleted layer created right at the interface of the gate and the dielectric. This effectively acts as a capacitor in series with the dielectric and increases what is called the "effective oxide thickness". This is very bad, especially when process engineers are trying extremely hard to reduce the oxide thickness. At the scales we are at now, every Angstrom counts. In metal gates, the carrier density is 1000X higher. This makes it much harder to deplete and you regain the 4 angstroms. This means either higher performance with the same gate dielectric thickness, or you can get the same performance and increase the dielectric thickness by 4A, thereby reducing the gate tunneling leakage current (and hence power) by an order of magnitude. This is a big deal.
(3) Some high dielectric constant materials (that are candidates to replace silicon dioxide) are not very compatible with polysilicon. This could mean either thermodynamic instability or interfacial charge created that "pins" the workfunction (and affects the switching threshold voltage of the transistor)
(4) In fully-depleted silicon on insulator (FD-SOI, or "depleted substrate transistor" in Intel parlance) transistors, the threshold voltage comes out wrong when using doped polysilicon gates. It makes the transistor either too slow or too leaky. There is a desperate need for tuning the threshold voltage by using a different workfunction which can be found in some metal gates.
Of course, metal gates aren't without their problems. (the predecessors of today's transistors had metal gates - hence the 'M' in CMOS - Complementary METAL Oxide Semiconductor - which were replaced by polysilicon gates for processing ease.) Inability to be easily patterned, withstand high processing temperatures, reliability issues are just a few of them.
You're quite right, you can't change the work function of a pure metal - but if you have a blend of materials, they will have to equilibrate, as the energies of the electrons in one material will have higher energies than the electrons in the other. Therefore, electrons will move from one material to the other like water flowing downhill, until the average energies of the electrons in the material are uniform between domains (or atoms) of the different materials. This yields a single Fermi level, which is described as the average energy of the electrons in the material. By varying the quantities of the materials (here, nickel and silicon), you can change the fermi level of the material, thereby changing the work function of the material. So, while you can't change the work function of a pure metal (you'd have to apply an impossibly obscene amount of charge to do so), you can make different blends.
-Looking for a job as a materials chemist or multivariat
That large cache for your UltraSparc-III is off chip. This is important to note because the bandwidth you get from the off-chip caches is much lower than the bandwidth of an on-chip cache. In fact, if you read the Ultrasparc-III systems specs you'll find that the bandwidth to the cache is comparable to the bandwidth to DRAM on a relatively cheap PC (the new Intel Canterwood/Springdale chipsets have a peak DRAM bandwidth of 6.4GB/sec)
If you need a 2MB cache you should consider a Xeon-MP which has just that. Couple this with a reasonably fast core and you should see some good performance for your application. Most x86 processors will have at least 1Mb of cache by the end of the year (Hammer, Prescott, Banias).
As you might imagine, on-chip caches are expensive. As a rule of thumb, the closer the memory is to the processor core, the more expensive it will be.
Your argument that SPARC is superior to x86 is weak. I've designed both kinds of processors and everything these days is basically RISC-like. The x86 code is translated into micro-ops that look like RISC. SPARC also has some stupid instructions and idioms. For example, register windows may seem like a good idea, but they really grow your register file and limit your frequency. Also, delayed branches are stupid and limit many things you can do. If I had to do another SPARC chip, I'd do some translation of my own into more efficient hardware-friendly micro-ops.
SPARC systems are nowhere near as competive as x86 systems. Their last niche of superiority with server workloads will disappear with the proliferation of Opteron systems.