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Clearspeed Makes Tall Claims for Future Chip
Josuah writes "ClearSpeed Technology announced today a new multithreaded array processor named the CS301. Their press release states the chip can achieve 25Gflops for only 3W of power. New Scientist and TechNewsWorld have articles on this chip, each with more information about the chip. I wondering if this is too good to be true." The key phrase is in the Wired story: "Soon to be in prototype, the chip...". "Soon to be in prototype" is synonymous with "does not exist".
Today it was announced that Duke Nukem Forever would be optimized to run on the new CS301 processor develpoed by a new firm called ClearSpeed Technology. It is said that with this newfound processing speed, Duke Nukem Forever will be the most realistic game ever realeased.
---- Move SIG...For great justice!
Chips are virtually fabricated and tested well before the first bit of silicon is etched....you can actually be pretty sure of both a chips performance and reliability just from simulations these days. Also, having to etch development chips constantly is both expensive and time consuming....so the longer you can leave a design in virtual space, the better.
-psy
As well as the fact that I've seen this press release trolled by AC's on Slashdot.
25Gflops on 3W? That must be some unorthodox technology at work there. Anyone hear anything about some research corporation finding an amazing processor in a robot from the future?
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I'm reminded of all the promises we heard for the Transmeta chip, only a fraction of which are being realized. And they have an actual product to demonstrate, mind you.
Yeah, it sounds like wishful thinking. I have little faith in processors from unknown companies that claim to do what Intel, AMD and IBM combined haven't yet been able to achieve.
... best case, and 128 K of cache.
Unless this thing is working on highly specialized data sets, it doesn't matter how much data the core can mow through if it can't get the data fast enough. Why do you think AMD and Intel are so obsessed with their memory interfaces? There's little difference between the Athlon and the Athlon 64 besides large data width and fancy memory / SMP interfaces.
You can make theoritical things on a VHDL simulator that you'll never be able to make into actual silicon. The real magic of companies like Intel, IBM, AMD, etc isn't designing an uber powerful chip, it's designing an uber powerful chip that can actually be realizied in silicon, and at a cost that makes it worth selling.
There has been more than one firm that has suffered from simulator disease. They get all caught up in making an awesome, ass-kicking theoritical design that will eclipse everything and everybody that they forget about physical limits of actual silicon. They then find, when they try to really implement the chip, it just can't be done.
The basic idea is to have lots of "processing elements" that are basically ALUs with a bit of additional smarts (for branches mainly). Each PE has its own memory. The main processor (probably not the PC CPU) tells each PE what to do. Thus the Single Instruction Multiple Data. Things are a bit more complex then this (branches, pointers, and a few other things cause some problems.) but not too much worse. PE to PE communication is also interesting (the Maspar was a toroid as I recall).
The two basic problems with this type of a design are:
There are also a huge number of other problems. Caches don't generally do a darn thing for massive SIMD computers (if one processing element misses, they all do.) The memory usually has two types of pointers (one to the PE memory and one to global memory). I may contact the company to see if they want to hire a short-term consultant. hummm.... Have PhD will travel?
As Nietsche famously said, "If you stare too long into the Abyss, 1d4 Tanar'ri of random type will attack you."
Everything old is new again... eventually.
From reading the articles, it seems it is indeed designed to be a math coprocessor. Since the Pentium came out, those have been out of style. The Pentium effectively included a 80487 on the same die, and on other architectures that was done even earlier. But now it comes back - only now the idea is a far more powerful coprocessor for scientific functions.
No, it's not going to be very helpful to the average users. But for those of us that spend a lot of time using our computers to do complex mathematical calculations, it could be damn helpful, if it turns out to be anywhere near as powerful as they claim it will be.
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Friends don't let friends enable ecmascript.
unfortunately for them, the proof is too big for them to fit in this margin...
-1, "1337" speak
... parallel processing units may perform a lot more ops/sec/watt than one single unit. The speed of a processor depends on the time required to charge and discharge the stray capacitances of its connects, and the impedance of its transistors increases as the drive voltage decreases so the RC time constant goes up and the speed goes down. However, the energy required to charge the capacitance scales as voltage squared, so by accepting a hit on the speed (due to the voltage drop) you can do the same calculation with less energy. Clearspeed seems to be taking parallelism to the sub-processor level in order to reduce heat loads; their operations may take longer to complete, but they can do more operations in the same time as long as the code can use the processors in parallel. Thus the emphasis on "multi-threaded", because it wouldn't work otherwise.
Scientists restrict study to entire physical universe; creationist
Maybe if we decide to model "Life, the Universe and Everything?"
No, just modelling the surf breaking on a beach would need several beowulf clusters of these chips. Or the flow of gas through an airplane turbine. Or the weather in a small region of planet Earth. There are many simulations of non-linear systems whose simulation require a lot more CPU power than is likely to be available on the near future.
And what about the human brain itself? Our current computers are still so far from the data processing capability in our brains that many people doubt it will be possible at all. Assume we have about 100 billion (10^11) neurons, and each neuron has about a thousand synapses. Assume the simulation of each synapse would need one hundred floating point operations per second. Therefore, to simulate the operation of a typical human brain one would need ten million Gflops, equivalent to a Beowulf cluster of 400000 of these chips. That's what it'll take to do the AI in Duke Nukem Whenever...
Onyxruby's law:
;) /me reminded of when apple tried claiming the imac as supercomputer.
The amount of hype per inch produced by marketing doubles every 18 months.
With apologies to Moore
Yes, I see...
Ordinary x86 by day, but SuperComputer by night. I wonder what the theme song will be...
It should read: "Clearspeed Makes Tall Claims for Fictional Chip"
I'm sure that cyberdyne chip is working out well for them... But what are they going to do with the arm? Juggling? Labyrinth-esque sphere stuff? I kinda shudder to think...
The big print giveth and the small print taketh away - Tom Waits
Some of the hardware design came from from engineers in Bristol, UK. Companies like Division and INMOS (anyone remember the T800 and T9000 transputer and a Microway board for parallel computing on a PC board more than a decade ago?). The other half of the design team came from UNC computer graphics lab in Chapel Hill. From the well known PixelFlow and PixelPlane machines. That along with a Taiwanese fab plant that would produce these SIMD processors with extra PE (SIMD Processor Engines) that would compensate for the manufacturing errors. eg. Lets say the chip would have 100 PEs so they would manufacture it 120 PEs. Those that didn't work they'd switch off and they wouldn't have to throw away the entire chip.
The story of PixelFusion was unfortunate. They could have rocked the computer graphics world with their scalable tile based rendering technology and efficient manufacturing methods. The programmable PEs would be able to handle both Direct X and Open GL. I suppose now they are trying to focus their investment and IP into more generic applications. I find their claims to be plausible because they have demonstrated innovative chips in the past.
My 2 cents
The chip will have 64 parallel FPU's. If it can complete one floating point operation per cycle, it will only need to run at about 350 to 400Mhz to reach 25GFLOPS (latency and pipeline issues aside, of course). Even if it requires 2 clock cycles, or the first 32 FPU's feed the second, we're talking about 700 to 800Mhz.
I'm not certain, but I thought I ran across similar number crunching capabilities in Integer OPS. It seems to me to have been in regards to fibre fabric and switching.
Or I could be on crack.
Hm.
Moekandu
Mediocrity knows nothing higher than itself; but talent instantly recognizes genius. -- Sir Arthur Conan Doyle
Here's the link.
graphics cards as general processors
Without a working prototype they have nothing.
With a working prototype they still have not much.
With a working, and cost-efficient manufacturing process, they have something.
When there are compilers that actually can use this kind of thing, it starts to be somthing that is real.
My guess is they are about a decade from a reliable, usable and cheap product. Suddenly these numbers do not sound impressive at all...
Most ACs are not even worth the keystrokes to insult them. Be generically insulted by this and ignored otherwise.
If I understand the article correctly, it looks like they're implementing a much more powerful version of Apple's Altivec SIMD technology. My question is, if computing power increases 500x using this technology, doesn't memory bandwidth and system bus speed have to increase exponentially as well just to realize any gains?
It seems like putting one of these cards in a PC with today's technology would be like sticking a mainframe behind a 300 baud connection: sure it can handle millions of transactions a second, but you'll never actually see that kind of throughput because memory is so slow.
"When the president does it, that means it's not illegal." - Richard M. Nixon
So I'll summarize some interesting key points:
1. The chip is fully programmable and an SDK invluding C compiler is available now.
2. The chip will be marketed as a coprocessor.
3. They expect to start selling them for around $16,000 in a few months.
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