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Clearspeed Makes Tall Claims for Future Chip

Posted by michael on from the pound-of-salt dept.

Josuah writes "ClearSpeed Technology announced today a new multithreaded array processor named the CS301. Their press release states the chip can achieve 25Gflops for only 3W of power. New Scientist and TechNewsWorld have articles on this chip, each with more information about the chip. I wondering if this is too good to be true." The key phrase is in the Wired story: "Soon to be in prototype, the chip...". "Soon to be in prototype" is synonymous with "does not exist".

8 of 254 comments (clear)

  1. In other news... by Ikeya · · Score: 3, Funny

    Today it was announced that Duke Nukem Forever would be optimized to run on the new CS301 processor develpoed by a new firm called ClearSpeed Technology. It is said that with this newfound processing speed, Duke Nukem Forever will be the most realistic game ever realeased.

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    ---- Move SIG...For great justice!
  2. "Soon to be in prototype" by psyconaut · · Score: 4, Informative

    Chips are virtually fabricated and tested well before the first bit of silicon is etched....you can actually be pretty sure of both a chips performance and reliability just from simulations these days. Also, having to etch development chips constantly is both expensive and time consuming....so the longer you can leave a design in virtual space, the better.

    -psy

  3. Skeptical by cybermace5 · · Score: 4, Funny

    As well as the fact that I've seen this press release trolled by AC's on Slashdot.

    25Gflops on 3W? That must be some unorthodox technology at work there. Anyone hear anything about some research corporation finding an amazing processor in a robot from the future?

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  4. echoes of Transmeta by mblase · · Score: 3, Insightful

    I'm reminded of all the promises we heard for the Transmeta chip, only a fraction of which are being realized. And they have an actual product to demonstrate, mind you.

    Yeah, it sounds like wishful thinking. I have little faith in processors from unknown companies that claim to do what Intel, AMD and IBM combined haven't yet been able to achieve.

  5. Maspar by hobit · · Score: 4, Interesting
    For the last 10 years or so I've been thinking about how to do just this. What I'm 99% sure they are doing is SIMD on a massive scale. The Maspar (and especially the Maspar-2) were computers along this line.

    The basic idea is to have lots of "processing elements" that are basically ALUs with a bit of additional smarts (for branches mainly). Each PE has its own memory. The main processor (probably not the PC CPU) tells each PE what to do. Thus the Single Instruction Multiple Data. Things are a bit more complex then this (branches, pointers, and a few other things cause some problems.) but not too much worse. PE to PE communication is also interesting (the Maspar was a toroid as I recall).

    The two basic problems with this type of a design are:

    • You either need a special programming language (and someone who understands the language and understands the problem really well) or a very very good compiler to get anything out of it.
    • The application range is quite limited. Not as limited as supercomputer people seem to think (I mean I've written genetic algorithm code for the Maspar that scales wonderfully.) but still quite limited.

    There are also a huge number of other problems. Caches don't generally do a darn thing for massive SIMD computers (if one processing element misses, they all do.) The memory usually has two types of pointers (one to the PE memory and one to global memory). I may contact the company to see if they want to hire a short-term consultant. hummm.... Have PhD will travel?

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    As Nietsche famously said, "If you stare too long into the Abyss, 1d4 Tanar'ri of random type will attack you."
  6. If I have the physics right... by Spamalamadingdong · · Score: 3, Interesting

    ... parallel processing units may perform a lot more ops/sec/watt than one single unit. The speed of a processor depends on the time required to charge and discharge the stray capacitances of its connects, and the impedance of its transistors increases as the drive voltage decreases so the RC time constant goes up and the speed goes down. However, the energy required to charge the capacitance scales as voltage squared, so by accepting a hit on the speed (due to the voltage drop) you can do the same calculation with less energy. Clearspeed seems to be taking parallelism to the sub-processor level in order to reduce heat loads; their operations may take longer to complete, but they can do more operations in the same time as long as the code can use the processors in parallel. Thus the emphasis on "multi-threaded", because it wouldn't work otherwise.

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    Scientists restrict study to entire physical universe; creationist
  7. Onyxruby's law by onyxruby · · Score: 3, Funny

    Onyxruby's law:

    The amount of hype per inch produced by marketing doubles every 18 months.

    With apologies to Moore ;) /me reminded of when apple tried claiming the imac as supercomputer.

  8. Plausible by saha · · Score: 3, Interesting
    Clearspeed formerly known as Pixelfusion was a promising graphics chip company that developed these scalable SIMD processors a few years ago. They put 24Mbits of RAM directly on to the chip, to have the enormous memory bandwidth that was and still is unheard of in the industry. After the industry attention shifted towards Nvidia, ATI, 3DLabs the board of directors reorganized the company to focus on high speed network switchers and routers.

    Some of the hardware design came from from engineers in Bristol, UK. Companies like Division and INMOS (anyone remember the T800 and T9000 transputer and a Microway board for parallel computing on a PC board more than a decade ago?). The other half of the design team came from UNC computer graphics lab in Chapel Hill. From the well known PixelFlow and PixelPlane machines. That along with a Taiwanese fab plant that would produce these SIMD processors with extra PE (SIMD Processor Engines) that would compensate for the manufacturing errors. eg. Lets say the chip would have 100 PEs so they would manufacture it 120 PEs. Those that didn't work they'd switch off and they wouldn't have to throw away the entire chip.

    The story of PixelFusion was unfortunate. They could have rocked the computer graphics world with their scalable tile based rendering technology and efficient manufacturing methods. The programmable PEs would be able to handle both Direct X and Open GL. I suppose now they are trying to focus their investment and IP into more generic applications. I find their claims to be plausible because they have demonstrated innovative chips in the past.

    My 2 cents